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| author | Denis Khalikov <khalikov.denis@huawei.com> | 2020-01-07 21:40:42 -0500 |
|---|---|---|
| committer | Lei Zhang <antiagainst@google.com> | 2020-01-07 21:45:54 -0500 |
| commit | 9883b14cd1a4ea2dec8d7ed30df632671f56c69b (patch) | |
| tree | 1fe789761ab23b8f32a3a692a59193e76d19decf /mlir/test/Dialect/SPIRV/Serialization | |
| parent | f7ca0c761979f0a06894571245a913cd8e2dbfce (diff) | |
| download | bcm5719-llvm-9883b14cd1a4ea2dec8d7ed30df632671f56c69b.tar.gz bcm5719-llvm-9883b14cd1a4ea2dec8d7ed30df632671f56c69b.zip | |
[mlir][spirv] Add lowering for standard bit ops
Differential Revision: https://reviews.llvm.org/D72205
Diffstat (limited to 'mlir/test/Dialect/SPIRV/Serialization')
| -rw-r--r-- | mlir/test/Dialect/SPIRV/Serialization/bit-ops.mlir | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/mlir/test/Dialect/SPIRV/Serialization/bit-ops.mlir b/mlir/test/Dialect/SPIRV/Serialization/bit-ops.mlir index fa823ea8a9d..9ca6174ec16 100644 --- a/mlir/test/Dialect/SPIRV/Serialization/bit-ops.mlir +++ b/mlir/test/Dialect/SPIRV/Serialization/bit-ops.mlir @@ -31,6 +31,15 @@ spv.module "Logical" "GLSL450" { %0 = spv.Not %arg : i32 spv.ReturnValue %0 : i32 } + func @bitwise_scalar(%arg0 : i32, %arg1 : i32) { + // CHECK: spv.BitwiseAnd + %0 = spv.BitwiseAnd %arg0, %arg1 : i32 + // CHECK: spv.BitwiseOr + %1 = spv.BitwiseOr %arg0, %arg1 : i32 + // CHECK: spv.BitwiseXor + %2 = spv.BitwiseXor %arg0, %arg1 : i32 + spv.Return + } func @shift_left_logical(%arg0: i32, %arg1 : i16) -> i32 { // CHECK: {{%.*}} = spv.ShiftLeftLogical {{%.*}}, {{%.*}} : i32, i16 %0 = spv.ShiftLeftLogical %arg0, %arg1: i32, i16 |
