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| author | Denis Khalikov <khalikov.denis@huawei.com> | 2019-11-08 11:05:32 -0800 |
|---|---|---|
| committer | A. Unique TensorFlower <gardener@tensorflow.org> | 2019-11-08 11:17:05 -0800 |
| commit | 4697d657b7927360e166efb12ff4e3bd6cc7b5db (patch) | |
| tree | fc0c77b65ef7b90113d67de6ba76a908f1cbca71 /mlir/test/Dialect/SPIRV/Serialization | |
| parent | 24f306a22b630349e4f94693822a134c15ac1612 (diff) | |
| download | bcm5719-llvm-4697d657b7927360e166efb12ff4e3bd6cc7b5db.tar.gz bcm5719-llvm-4697d657b7927360e166efb12ff4e3bd6cc7b5db.zip | |
[spirv] Add bit ops
This CL added op definitions for a few bit operations:
* OpShiftLeftLogical
* OpShiftRightArithmetic
* OpShiftRightLogical
* OpBitCount
* OpBitReverse
* OpNot
Also moved the definition of spv.BitwiseAnd to follow the
lexicographical order.
Closes tensorflow/mlir#215
COPYBARA_INTEGRATE_REVIEW=https://github.com/tensorflow/mlir/pull/215 from denis0x0D:sandbox/bit_ops d9b0852b689ac6c4879a9740b1740a2357f44d24
PiperOrigin-RevId: 279350470
Diffstat (limited to 'mlir/test/Dialect/SPIRV/Serialization')
| -rw-r--r-- | mlir/test/Dialect/SPIRV/Serialization/bit-ops.td | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/mlir/test/Dialect/SPIRV/Serialization/bit-ops.td b/mlir/test/Dialect/SPIRV/Serialization/bit-ops.td new file mode 100644 index 00000000000..a1ca154ec7f --- /dev/null +++ b/mlir/test/Dialect/SPIRV/Serialization/bit-ops.td @@ -0,0 +1,34 @@ +// RUN: mlir-translate -test-spirv-roundtrip -split-input-file %s | FileCheck %s + +spv.module "Logical" "GLSL450" { + func @bitcount(%arg: i32) -> i32 { + // CHECK: spv.BitCount {{%.*}} : i32 + %0 = spv.BitCount %arg : i32 + spv.ReturnValue %0 : i32 + } + func @bitreverse(%arg: i32) -> i32 { + // CHECK: spv.BitReverse {{%.*}} : i32 + %0 = spv.BitReverse %arg : i32 + spv.ReturnValue %0 : i32 + } + func @not(%arg: i32) -> i32 { + // CHECK: spv.Not {{%.*}} : i32 + %0 = spv.Not %arg : i32 + spv.ReturnValue %0 : i32 + } + func @shift_left_logical(%arg0: i32, %arg1 : i16) -> i32 { + // CHECK: {{%.*}} = spv.ShiftLeftLogical {{%.*}}, {{%.*}} : i32, i16 + %0 = spv.ShiftLeftLogical %arg0, %arg1: i32, i16 + spv.ReturnValue %0 : i32 + } + func @shift_right_aritmethic(%arg0: vector<4xi32>, %arg1 : vector<4xi8>) -> vector<4xi32> { + // CHECK: {{%.*}} = spv.ShiftRightArithmetic {{%.*}}, {{%.*}} : vector<4xi32>, vector<4xi8> + %0 = spv.ShiftRightArithmetic %arg0, %arg1: vector<4xi32>, vector<4xi8> + spv.ReturnValue %0 : vector<4xi32> + } + func @shift_right_logical(%arg0: vector<2xi32>, %arg1 : vector<2xi8>) -> vector<2xi32> { + // CHECK: {{%.*}} = spv.ShiftRightLogical {{%.*}}, {{%.*}} : vector<2xi32>, vector<2xi8> + %0 = spv.ShiftRightLogical %arg0, %arg1: vector<2xi32>, vector<2xi8> + spv.ReturnValue %0 : vector<2xi32> + } +} |

