diff options
author | River Riddle <riverriddle@google.com> | 2019-12-23 11:18:53 -0800 |
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committer | A. Unique TensorFlower <gardener@tensorflow.org> | 2019-12-23 15:44:00 -0800 |
commit | f603a50109107b447b835dac11f0eb541288393e (patch) | |
tree | a36f5e8e36cb4408819a9f7ab570fda449558e5f /mlir/lib/Dialect | |
parent | 56222a0694e4caf35e892d70591417c39fef1185 (diff) | |
download | bcm5719-llvm-f603a50109107b447b835dac11f0eb541288393e.tar.gz bcm5719-llvm-f603a50109107b447b835dac11f0eb541288393e.zip |
ReImplement the Value classes as value-typed objects wrapping an internal pointer storage.
This will enable future commits to reimplement the internal implementation of OpResult without needing to change all of the existing users. This is part of a chain of commits optimizing the size of operation results.
PiperOrigin-RevId: 286919966
Diffstat (limited to 'mlir/lib/Dialect')
-rw-r--r-- | mlir/lib/Dialect/AffineOps/AffineOps.cpp | 6 | ||||
-rw-r--r-- | mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp | 4 | ||||
-rw-r--r-- | mlir/lib/Dialect/LoopOps/LoopOps.cpp | 2 | ||||
-rw-r--r-- | mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp | 2 |
4 files changed, 7 insertions, 7 deletions
diff --git a/mlir/lib/Dialect/AffineOps/AffineOps.cpp b/mlir/lib/Dialect/AffineOps/AffineOps.cpp index bfe72101e85..d80f9865ccb 100644 --- a/mlir/lib/Dialect/AffineOps/AffineOps.cpp +++ b/mlir/lib/Dialect/AffineOps/AffineOps.cpp @@ -107,7 +107,7 @@ static bool isFunctionRegion(Region *region) { /// function. A value of index type defined at the top level is always a valid /// symbol. bool mlir::isTopLevelValue(ValuePtr value) { - if (auto arg = dyn_cast<BlockArgument>(value)) + if (auto arg = value.dyn_cast<BlockArgument>()) return isFunctionRegion(arg->getOwner()->getParent()); return isFunctionRegion(value->getDefiningOp()->getParentRegion()); } @@ -134,7 +134,7 @@ bool mlir::isValidDim(ValuePtr value) { return false; } // This value has to be a block argument for a FuncOp or an affine.for. - auto *parentOp = cast<BlockArgument>(value)->getOwner()->getParentOp(); + auto *parentOp = value.cast<BlockArgument>()->getOwner()->getParentOp(); return isa<FuncOp>(parentOp) || isa<AffineForOp>(parentOp); } @@ -1571,7 +1571,7 @@ bool mlir::isForInductionVar(ValuePtr val) { /// Returns the loop parent of an induction variable. If the provided value is /// not an induction variable, then return nullptr. AffineForOp mlir::getForInductionVarOwner(ValuePtr val) { - auto ivArg = dyn_cast<BlockArgument>(val); + auto ivArg = val.dyn_cast<BlockArgument>(); if (!ivArg || !ivArg->getOwner()) return AffineForOp(); auto *containingInst = ivArg->getOwner()->getParent()->getParentOp(); diff --git a/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp b/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp index 5fbbdea60c2..be90b1ce5a6 100644 --- a/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp +++ b/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp @@ -41,7 +41,7 @@ static StringRef toStringRef(LinalgDependenceGraph::DependenceType dt) { } ValuePtr Aliases::find(ValuePtr v) { - if (isa<BlockArgument>(v)) + if (v.isa<BlockArgument>()) return v; auto it = aliases.find(v); @@ -51,7 +51,7 @@ ValuePtr Aliases::find(ValuePtr v) { } while (true) { - if (isa<BlockArgument>(v)) + if (v.isa<BlockArgument>()) return v; if (auto alloc = dyn_cast_or_null<AllocOp>(v->getDefiningOp())) { if (isStrided(alloc.getType())) diff --git a/mlir/lib/Dialect/LoopOps/LoopOps.cpp b/mlir/lib/Dialect/LoopOps/LoopOps.cpp index d3040c1bbb2..8e19eba911a 100644 --- a/mlir/lib/Dialect/LoopOps/LoopOps.cpp +++ b/mlir/lib/Dialect/LoopOps/LoopOps.cpp @@ -136,7 +136,7 @@ LogicalResult ForOp::moveOutOfLoop(ArrayRef<Operation *> ops) { } ForOp mlir::loop::getForInductionVarOwner(ValuePtr val) { - auto ivArg = dyn_cast<BlockArgument>(val); + auto ivArg = val.dyn_cast<BlockArgument>(); if (!ivArg) return ForOp(); assert(ivArg->getOwner() && "unlinked block argument"); diff --git a/mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp b/mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp index 7ff471dfda5..424c2e0427e 100644 --- a/mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp +++ b/mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp @@ -509,7 +509,7 @@ void Serializer::printValueIDMap(raw_ostream &os) { << "id = " << valueIDPair.second << ' '; if (auto *op = val->getDefiningOp()) { os << "from op '" << op->getName() << "'"; - } else if (auto arg = dyn_cast<BlockArgument>(val)) { + } else if (auto arg = val.dyn_cast<BlockArgument>()) { Block *block = arg->getOwner(); os << "from argument of block " << block << ' '; os << " in op '" << block->getParentOp()->getName() << "'"; |