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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-19 19:08:03 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-19 19:08:03 +0000 |
| commit | ff7beb17547968a0232e12ac08d07f27a0713b51 (patch) | |
| tree | 22abfe6ad831ab074d1363cd737c968d24c9e374 /llvm | |
| parent | 41f54dc482479fe6de61e00452de55d3be474373 (diff) | |
| download | bcm5719-llvm-ff7beb17547968a0232e12ac08d07f27a0713b51.tar.gz bcm5719-llvm-ff7beb17547968a0232e12ac08d07f27a0713b51.zip | |
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
llvm-svn: 188690
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsCondMov.td | 15 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips-fpu-instructions.s | 1 |
2 files changed, 10 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/MipsCondMov.td b/llvm/lib/Target/Mips/MipsCondMov.td index b313c52178b..1f19adc326d 100644 --- a/llvm/lib/Target/Mips/MipsCondMov.td +++ b/llvm/lib/Target/Mips/MipsCondMov.td @@ -148,15 +148,17 @@ let Predicates = [NotFP64bit, HasStdEnc] in { CMov_I_F_FM<19, 17>; } -let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in { +let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, IIFmove>, CMov_I_F_FM<18, 17>; - def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, - IIFmove>, CMov_I_F_FM<18, 17>; def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, IIFmove>, CMov_I_F_FM<19, 17>; - def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, - IIFmove>, CMov_I_F_FM<19, 17>; + let isCodeGenOnly = 1 in { + def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, + IIFmove>, CMov_I_F_FM<18, 17>; + def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, + IIFmove>, CMov_I_F_FM<19, 17>; + } } def MOVT_I : CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>, @@ -184,7 +186,8 @@ let Predicates = [NotFP64bit, HasStdEnc] in { def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64Opnd, IIFmove, MipsCMovFP_F>, CMov_F_F_FM<17, 0>; } -let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in { + +let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, IIFmove, MipsCMovFP_T>, CMov_F_F_FM<17, 1>; def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, IIFmove, MipsCMovFP_F>, diff --git a/llvm/test/MC/Mips/mips-fpu-instructions.s b/llvm/test/MC/Mips/mips-fpu-instructions.s index dc52676433e..0a240d224af 100644 --- a/llvm/test/MC/Mips/mips-fpu-instructions.s +++ b/llvm/test/MC/Mips/mips-fpu-instructions.s @@ -1,4 +1,5 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s +# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s # Check that the assembler can handle the documented syntax # for FPU instructions. #------------------------------------------------------------------------------ |
