[X86] Don't set the operation action for i16 SINT_TO_FP to Promote just because SSE1 is enabled.

Instead do custom promotion in the handler so that we can still
allow i16 to be used with fp80. And f64 without sse2.

3 files changed, 44 insertions, 45 deletions

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9b4571af283..fff0d7d8b3f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -238,9 +238,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
     // this operation.
     setOperationAction(ISD::SINT_TO_FP, MVT::i8,  Promote);
-    // SSE has no i16 to fp conversion, only i32.
-    setOperationAction(ISD::SINT_TO_FP, MVT::i16, X86ScalarSSEf32 ? Promote
-                                                                  : Custom);
+    // SSE has no i16 to fp conversion, only i32. We promote in the handler
+    // to allow f80 to use i16 and f64 to use i16 with sse1 only
+    setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
     // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
     setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
     // In 32-bit mode these are custom lowered.  In 64-bit mode F32 and F64
@@ -18441,6 +18441,12 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
   if (SDValue V = LowerI64IntToFP_AVX512DQ(Op, DAG, Subtarget))
     return V;
 
+  // SSE doesn't have an i16 conversion so we need to promote.
+  if (SrcVT == MVT::i16 && isScalarFPTypeInSSEReg(VT)) {
+    SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, Src);
+    return DAG.getNode(ISD::SINT_TO_FP, dl, VT, Ext);
+  }
+
   SDValue ValueToStore = Op.getOperand(0);
   if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(VT) &&
       !Subtarget.is64Bit())
diff --git a/llvm/test/CodeGen/X86/fp-arith.ll b/llvm/test/CodeGen/X86/fp-arith.ll
index 73a132da304..8f1ce43a8f6 100644
--- a/llvm/test/CodeGen/X86/fp-arith.ll
+++ b/llvm/test/CodeGen/X86/fp-arith.ll
@@ -22,9 +22,8 @@ define x86_fp80 @fiadd_fp80_i16(x86_fp80 %a0, i16 %a1) {
 ; X64-LABEL: fiadd_fp80_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl %di, %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fiaddl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fiadds -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = sitofp i16 %a1 to x86_fp80
   %2 = fadd x86_fp80 %a0, %1
@@ -48,9 +47,9 @@ define x86_fp80 @fiadd_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
 ; X64-LABEL: fiadd_fp80_i16_ld:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl (%rdi), %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fiaddl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movzwl (%rdi), %eax
+; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fiadds -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = load i16, i16 *%a1
   %2 = sitofp i16 %1 to x86_fp80
@@ -129,9 +128,8 @@ define x86_fp80 @fisub_fp80_i16(x86_fp80 %a0, i16 %a1) {
 ; X64-LABEL: fisub_fp80_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl %di, %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fisubl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fisubs -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = sitofp i16 %a1 to x86_fp80
   %2 = fsub x86_fp80 %a0, %1
@@ -155,9 +153,9 @@ define x86_fp80 @fisub_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
 ; X64-LABEL: fisub_fp80_i16_ld:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl (%rdi), %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fisubl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movzwl (%rdi), %eax
+; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fisubs -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = load i16, i16 *%a1
   %2 = sitofp i16 %1 to x86_fp80
@@ -236,9 +234,8 @@ define x86_fp80 @fisubr_fp80_i16(x86_fp80 %a0, i16 %a1) {
 ; X64-LABEL: fisubr_fp80_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl %di, %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fisubrl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fisubrs -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = sitofp i16 %a1 to x86_fp80
   %2 = fsub x86_fp80 %1, %a0
@@ -262,9 +259,9 @@ define x86_fp80 @fisubr_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
 ; X64-LABEL: fisubr_fp80_i16_ld:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl (%rdi), %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fisubrl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movzwl (%rdi), %eax
+; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fisubrs -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = load i16, i16 *%a1
   %2 = sitofp i16 %1 to x86_fp80
@@ -343,9 +340,8 @@ define x86_fp80 @fimul_fp80_i16(x86_fp80 %a0, i16 %a1) {
 ; X64-LABEL: fimul_fp80_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl %di, %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fimull -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fimuls -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = sitofp i16 %a1 to x86_fp80
   %2 = fmul x86_fp80 %a0, %1
@@ -369,9 +365,9 @@ define x86_fp80 @fimul_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
 ; X64-LABEL: fimul_fp80_i16_ld:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl (%rdi), %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fimull -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movzwl (%rdi), %eax
+; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fimuls -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = load i16, i16 *%a1
   %2 = sitofp i16 %1 to x86_fp80
@@ -450,9 +446,8 @@ define x86_fp80 @fidiv_fp80_i16(x86_fp80 %a0, i16 %a1) {
 ; X64-LABEL: fidiv_fp80_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl %di, %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fidivl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fidivs -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = sitofp i16 %a1 to x86_fp80
   %2 = fdiv x86_fp80 %a0, %1
@@ -476,9 +471,9 @@ define x86_fp80 @fidiv_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
 ; X64-LABEL: fidiv_fp80_i16_ld:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl (%rdi), %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fidivl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movzwl (%rdi), %eax
+; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fidivs -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = load i16, i16 *%a1
   %2 = sitofp i16 %1 to x86_fp80
@@ -557,9 +552,8 @@ define x86_fp80 @fidivr_fp80_i16(x86_fp80 %a0, i16 %a1) {
 ; X64-LABEL: fidivr_fp80_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl %di, %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fidivrl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fidivrs -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = sitofp i16 %a1 to x86_fp80
   %2 = fdiv x86_fp80 %1, %a0
@@ -583,9 +577,9 @@ define x86_fp80 @fidivr_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
 ; X64-LABEL: fidivr_fp80_i16_ld:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
-; X64-NEXT:    movswl (%rdi), %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fidivrl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movzwl (%rdi), %eax
+; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    fidivrs -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = load i16, i16 *%a1
   %2 = sitofp i16 %1 to x86_fp80
diff --git a/llvm/test/CodeGen/X86/fp-cvt.ll b/llvm/test/CodeGen/X86/fp-cvt.ll
index 8164651f996..8b271ae77c1 100644
--- a/llvm/test/CodeGen/X86/fp-cvt.ll
+++ b/llvm/test/CodeGen/X86/fp-cvt.ll
@@ -615,9 +615,8 @@ define x86_fp80 @sitofp_fp80_i16(i16 %a0) nounwind {
 ;
 ; X64-LABEL: sitofp_fp80_i16:
 ; X64:       # %bb.0:
-; X64-NEXT:    movswl %di, %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fildl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movw %di, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    filds -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = sitofp i16 %a0 to x86_fp80
   ret x86_fp80 %1
@@ -636,9 +635,9 @@ define x86_fp80 @sitofp_fp80_i16_ld(i16 *%a0) nounwind {
 ;
 ; X64-LABEL: sitofp_fp80_i16_ld:
 ; X64:       # %bb.0:
-; X64-NEXT:    movswl (%rdi), %eax
-; X64-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT:    fildl -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movzwl (%rdi), %eax
+; X64-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    filds -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = load i16, i16 *%a0
   %2 = sitofp i16 %1 to x86_fp80