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| author | Diana Picus <diana.picus@linaro.org> | 2018-01-30 09:15:27 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2018-01-30 09:15:27 +0000 |
| commit | f72e8653722512e3d157c607c6cbfd8223855770 (patch) | |
| tree | f601c2390fc90a0b7176aa586f718cae8ef8e362 /llvm | |
| parent | 2a5b96203024a0d2da6bf10c7ac205f51632513a (diff) | |
| download | bcm5719-llvm-f72e8653722512e3d157c607c6cbfd8223855770.tar.gz bcm5719-llvm-f72e8653722512e3d157c607c6cbfd8223855770.zip | |
[ARM GlobalISel] Add inst selector tests for G_SITOFP and G_UITOFP
These are handled by the TableGen'erated code.
llvm-svn: 323732
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index 83dd5447411..db7cb7a0939 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -38,6 +38,11 @@ define void @test_fptoui_s32() #0 { ret void } define void @test_fptoui_s64() #0 { ret void } + define void @test_sitofp_s32() #0 { ret void } + define void @test_sitofp_s64() #0 { ret void } + define void @test_uitofp_s32() #0 { ret void } + define void @test_uitofp_s64() #0 { ret void } + define void @test_sub_s32() { ret void } define void @test_sub_imm_s32() { ret void } define void @test_sub_rev_imm_s32() { ret void } @@ -898,6 +903,114 @@ body: | ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- +name: test_sitofp_s32 +# CHECK-LABEL: name: test_sitofp_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: fprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 + + %1(s32) = G_SITOFP %0(s32) + ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] + ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, %noreg + + %s0 = COPY %1(s32) + ; CHECK: %s0 = COPY [[VREGR]] + + BX_RET 14, %noreg, implicit %s0 + ; CHECK: BX_RET 14, %noreg, implicit %s0 +... +--- +name: test_sitofp_s64 +# CHECK-LABEL: name: test_sitofp_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: fprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 + + %1(s64) = G_SITOFP %0(s32) + ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] + ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, %noreg + + %d0 = COPY %1(s64) + ; CHECK: %d0 = COPY [[VREGR]] + + BX_RET 14, %noreg, implicit %d0 + ; CHECK: BX_RET 14, %noreg, implicit %d0 +... +--- +name: test_uitofp_s32 +# CHECK-LABEL: name: test_uitofp_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: fprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 + + %1(s32) = G_UITOFP %0(s32) + ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] + ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, %noreg + + %s0 = COPY %1(s32) + ; CHECK: %s0 = COPY [[VREGR]] + + BX_RET 14, %noreg, implicit %s0 + ; CHECK: BX_RET 14, %noreg, implicit %s0 +... +--- +name: test_uitofp_s64 +# CHECK-LABEL: name: test_uitofp_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: fprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 + + %1(s64) = G_UITOFP %0(s32) + ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] + ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, %noreg + + %d0 = COPY %1(s64) + ; CHECK: %d0 = COPY [[VREGR]] + + BX_RET 14, %noreg, implicit %d0 + ; CHECK: BX_RET 14, %noreg, implicit %d0 +... +--- name: test_sub_s32 # CHECK-LABEL: name: test_sub_s32 legalized: true |
