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| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-06-17 14:31:51 +0000 |
|---|---|---|
| committer | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-06-17 14:31:51 +0000 |
| commit | f712ede932b5e1931411266583f20d20dc64fa0d (patch) | |
| tree | d57fc38a4fda97f1c18ce7b3e9aa6951bc0bf27a /llvm | |
| parent | 71c9257f0781dcaf56462071b5107e11e937271f (diff) | |
| download | bcm5719-llvm-f712ede932b5e1931411266583f20d20dc64fa0d.tar.gz bcm5719-llvm-f712ede932b5e1931411266583f20d20dc64fa0d.zip | |
[mips] [IAS] Add support for expanding LASym with a source register operand.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D9348
llvm-svn: 239910
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 31 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips-expansions.s | 6 |
2 files changed, 25 insertions, 12 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 80a0de1105e..5b8d633554b 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -186,9 +186,9 @@ class MipsAsmParser : public MCTargetAsmParser { bool Is32BitImm, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions); - bool loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, - bool Is32BitSym, SMLoc IDLoc, - SmallVectorImpl<MCInst> &Instructions); + bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, + unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc, + SmallVectorImpl<MCInst> &Instructions); bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions); @@ -1929,18 +1929,20 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, const MCOperand &DstRegOp = Inst.getOperand(0); assert(DstRegOp.isReg() && "expected register operand kind"); + const MCOperand &SrcRegOp = Inst.getOperand(1); + assert(SrcRegOp.isReg() && "expected register operand kind"); + const MCOperand &ImmOp = Inst.getOperand(2); assert((ImmOp.isImm() || ImmOp.isExpr()) && "expected immediate operand kind"); if (!ImmOp.isImm()) { - if (loadSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), Is32BitImm, IDLoc, - Instructions)) + if (loadAndAddSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), + SrcRegOp.getReg(), Is32BitImm, IDLoc, + Instructions)) return true; return false; } - const MCOperand &SrcRegOp = Inst.getOperand(1); - assert(SrcRegOp.isReg() && "expected register operand kind"); if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(), Is32BitImm, IDLoc, Instructions)) @@ -1959,8 +1961,9 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, assert((ImmOp.isImm() || ImmOp.isExpr()) && "expected immediate operand kind"); if (!ImmOp.isImm()) { - if (loadSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), Is32BitImm, IDLoc, - Instructions)) + if (loadAndAddSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), + Mips::NoRegister, Is32BitImm, IDLoc, + Instructions)) return true; return false; @@ -1973,9 +1976,9 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, return false; } -bool MipsAsmParser::loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, - bool Is32BitSym, SMLoc IDLoc, - SmallVectorImpl<MCInst> &Instructions) { +bool MipsAsmParser::loadAndAddSymbolAddress( + const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym, + SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { warnIfNoMacro(IDLoc); if (Is32BitSym && isABI_N64()) @@ -2024,6 +2027,10 @@ bool MipsAsmParser::loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, createLShiftOri<0>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(), Instructions); } + + if (SrcReg != Mips::NoRegister) + createAddu(DstReg, DstReg, SrcReg, Instructions); + return false; } diff --git a/llvm/test/MC/Mips/mips-expansions.s b/llvm/test/MC/Mips/mips-expansions.s index 7e5e2e0a4d3..bae446cea2a 100644 --- a/llvm/test/MC/Mips/mips-expansions.s +++ b/llvm/test/MC/Mips/mips-expansions.s @@ -43,6 +43,12 @@ # CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 # CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] # CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 + la $8, symbol($9) +# CHECK: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] +# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] +# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK: addu $8, $8, $9 # encoding: [0x21,0x40,0x09,0x01] # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst(): .set noat |
