[mips] Reorder template parameters. Remove class shift_rotate_imm32 and

shift_rotate_imm64.

llvm-svn: 171513

2 files changed, 59 insertions, 54 deletions

diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index 2a1ed3a58c6..3961dd63b2c 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -34,11 +34,7 @@ def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
 //===----------------------------------------------------------------------===//
 // Instructions specific format
 //===----------------------------------------------------------------------===//
-// Shifts
-// 64-bit shift instructions.
 let DecoderNamespace = "Mips64" in {
-class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>:
-  shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>;
 
 multiclass Atomic2Ops64<PatFrag Op> {
   def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>,
@@ -102,37 +98,41 @@ def XOR64  : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
 def NOR64  : LogicNOR<"nor", CPU64Regs>, ADD_FM<0, 0x27>;
 
 /// Shift Instructions
-def DSLL   : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>;
-def DSRL   : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>;
-def DSRA   : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>;
-def DSLLV  : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>;
-def DSRLV  : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>;
-def DSRAV  : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>;
-def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>;
-def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>;
-def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>;
+def DSLL   : shift_rotate_imm<"dsll", shamt, CPU64Regs, shl, immZExt6>,
+             SRA_FM<0x38, 0>;
+def DSRL   : shift_rotate_imm<"dsrl", shamt, CPU64Regs, srl, immZExt6>,
+             SRA_FM<0x3a, 0>;
+def DSRA   : shift_rotate_imm<"dsra", shamt, CPU64Regs, sra, immZExt6>,
+             SRA_FM<0x3b, 0>;
+def DSLLV  : shift_rotate_reg<"dsllv", CPU64Regs, shl>, SRLV_FM<0x14, 0>;
+def DSRLV  : shift_rotate_reg<"dsrlv", CPU64Regs, srl>, SRLV_FM<0x16, 0>;
+def DSRAV  : shift_rotate_reg<"dsrav", CPU64Regs, sra>, SRLV_FM<0x17, 0>;
+def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64Regs>, SRA_FM<0x3c, 0>;
+def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64Regs>, SRA_FM<0x3e, 0>;
+def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64Regs>, SRA_FM<0x3f, 0>;
 }
 // Rotate Instructions
 let Predicates = [HasMips64r2, HasStdEnc],
     DecoderNamespace = "Mips64" in {
-  def DROTR  : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>;
-  def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>;
+  def DROTR  : shift_rotate_imm<"drotr", shamt, CPU64Regs, rotr, immZExt6>,
+                SRA_FM<0x3a, 1>;
+  def DROTRV : shift_rotate_reg<"drotrv", CPU64Regs, rotr>, SRLV_FM<0x16, 1>;
 }
 
 let DecoderNamespace = "Mips64" in {
 /// Load and Store Instructions
 ///  aligned
-defm LB64  : LoadM<"lb", sextloadi8, CPU64Regs>, LW_FM<0x20>;
-defm LBu64 : LoadM<"lbu", zextloadi8, CPU64Regs>, LW_FM<0x24>;
-defm LH64  : LoadM<"lh", sextloadi16, CPU64Regs>, LW_FM<0x21>;
-defm LHu64 : LoadM<"lhu", zextloadi16, CPU64Regs>, LW_FM<0x25>;
-defm LW64  : LoadM<"lw", sextloadi32, CPU64Regs>, LW_FM<0x23>;
-defm LWu64 : LoadM<"lwu", zextloadi32, CPU64Regs>, LW_FM<0x27>;
-defm SB64  : StoreM<"sb", truncstorei8, CPU64Regs>, LW_FM<0x28>;
-defm SH64  : StoreM<"sh", truncstorei16, CPU64Regs>, LW_FM<0x29>;
-defm SW64  : StoreM<"sw", truncstorei32, CPU64Regs>, LW_FM<0x2b>;
-defm LD    : LoadM<"ld", load, CPU64Regs>, LW_FM<0x37>;
-defm SD    : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>;
+defm LB64  : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>;
+defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>;
+defm LH64  : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>;
+defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>;
+defm LW64  : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>;
+defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>;
+defm SB64  : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>;
+defm SH64  : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>;
+defm SW64  : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>;
+defm LD    : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>;
+defm SD    : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>;
 
 /// load/store left/right
 let isCodeGenOnly = 1 in {
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 15c1fcc603d..f52ca52060e 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -340,6 +340,8 @@ class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0,
          [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> {
   let isCommutable = isComm;
   let isReMaterializable = 1;
+  string BaseOpcode;
+  string Arch;
 }
 
 // Arithmetic and logical instructions with 2 register operands.
@@ -353,7 +355,7 @@ class ArithLogicI<string opstr, Operand Od, RegisterClass RC,
 }
 
 // Arithmetic Multiply ADD/SUB
-class MArithR<string opstr, SDNode op, bit isComm = 0> :
+class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> :
   InstSE<(outs), (ins CPURegs:$rs, CPURegs:$rt),
          !strconcat(opstr, "\t$rs, $rt"),
          [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul, FrmR> {
@@ -371,17 +373,15 @@ class LogicNOR<string opstr, RegisterClass RC>:
 }
 
 // Shifts
-class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd,
-                       RegisterClass RC, SDPatternOperator OpNode> :
+class shift_rotate_imm<string opstr, Operand ImmOpnd,
+                       RegisterClass RC, SDPatternOperator OpNode = null_frag,
+                       SDPatternOperator PF = null_frag> :
   InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
          !strconcat(opstr, "\t$rd, $rt, $shamt"),
          [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
 
-// 32-bit shift instructions.
-class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> :
-  shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>;
-
-class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>:
+class shift_rotate_reg<string opstr, RegisterClass RC,
+                       SDPatternOperator OpNode = null_frag>:
   InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
          !strconcat(opstr, "\t$rd, $rt, $rs"),
          [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>;
@@ -403,20 +403,23 @@ class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
 }
 
 // Memory Load/Store
-class Load<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> :
+class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
+           Operand MemOpnd> :
   InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
          [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMem";
   let canFoldAsLoad = 1;
 }
 
-class Store<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> :
+class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
+            Operand MemOpnd> :
   InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
          [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMem";
 }
 
-multiclass LoadM<string opstr, PatFrag OpNode, RegisterClass RC> {
+multiclass LoadM<string opstr, RegisterClass RC,
+                 SDPatternOperator OpNode = null_frag> {
   def #NAME# : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
   def _P8    : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
     let DecoderNamespace = "Mips64";
@@ -424,7 +427,8 @@ multiclass LoadM<string opstr, PatFrag OpNode, RegisterClass RC> {
   }
 }
 
-multiclass StoreM<string opstr, PatFrag OpNode, RegisterClass RC> {
+multiclass StoreM<string opstr, RegisterClass RC,
+                  SDPatternOperator OpNode = null_frag> {
   def #NAME# : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
   def _P8    : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
     let DecoderNamespace = "Mips64";
@@ -789,29 +793,30 @@ def XOR  : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
 def NOR  : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>;
 
 /// Shift Instructions
-def SLL  : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>;
-def SRL  : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>;
-def SRA  : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>;
-def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>;
-def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>;
-def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>;
+def SLL  : shift_rotate_imm<"sll", shamt, CPURegs, shl, immZExt5>, SRA_FM<0, 0>;
+def SRL  : shift_rotate_imm<"srl", shamt, CPURegs, srl, immZExt5>, SRA_FM<2, 0>;
+def SRA  : shift_rotate_imm<"sra", shamt, CPURegs, sra, immZExt5>, SRA_FM<3, 0>;
+def SLLV : shift_rotate_reg<"sllv", CPURegs, shl>, SRLV_FM<4, 0>;
+def SRLV : shift_rotate_reg<"srlv", CPURegs, srl>, SRLV_FM<6, 0>;
+def SRAV : shift_rotate_reg<"srav", CPURegs, sra>, SRLV_FM<7, 0>;
 
 // Rotate Instructions
 let Predicates = [HasMips32r2, HasStdEnc] in {
-  def ROTR  : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>;
-  def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>;
+  def ROTR  : shift_rotate_imm<"rotr", shamt, CPURegs, rotr, immZExt5>,
+              SRA_FM<2, 1>;
+  def ROTRV : shift_rotate_reg<"rotrv", CPURegs, rotr>, SRLV_FM<6, 1>;
 }
 
 /// Load and Store Instructions
 ///  aligned
-defm LB  : LoadM<"lb", sextloadi8, CPURegs>, LW_FM<0x20>;
-defm LBu : LoadM<"lbu", zextloadi8, CPURegs>, LW_FM<0x24>;
-defm LH  : LoadM<"lh", sextloadi16, CPURegs>, LW_FM<0x21>;
-defm LHu : LoadM<"lhu", zextloadi16, CPURegs>, LW_FM<0x25>;
-defm LW  : LoadM<"lw", load, CPURegs>, LW_FM<0x23>;
-defm SB  : StoreM<"sb", truncstorei8, CPURegs>, LW_FM<0x28>;
-defm SH  : StoreM<"sh", truncstorei16, CPURegs>, LW_FM<0x29>;
-defm SW  : StoreM<"sw", store, CPURegs>, LW_FM<0x2b>;
+defm LB  : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>;
+defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>;
+defm LH  : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>;
+defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>;
+defm LW  : LoadM<"lw", CPURegs, load>, LW_FM<0x23>;
+defm SB  : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>;
+defm SH  : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>;
+defm SW  : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>;
 
 /// load/store left/right
 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;