Size reducing SP adjusting t2ADDri needs to check predication.

tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."

llvm-svn: 134130

1 files changed, 4 insertions, 1 deletions

diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
index 65846b24221..cb44f8e71c4 100644
--- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -491,11 +491,14 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
     // Try to reduce to tADDrSPi.
     unsigned Imm = MI->getOperand(2).getImm();
     // The immediate must be in range, the destination register must be a low
-    // reg, and the condition flags must not be being set.
+    // reg, the predicate must be "always" and the condition flags must not
+    // be being set.
     if (Imm & 3 || Imm > 1024)
       return false;
     if (!isARMLowRegister(MI->getOperand(0).getReg()))
       return false;
+    if (MI->getOperand(3).getImm() != ARMCC::AL)
+      return false;
     const MCInstrDesc &MCID = MI->getDesc();
     if (MCID.hasOptionalDef() &&
         MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)