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authorEvan Cheng <evan.cheng@apple.com>2009-07-25 01:55:25 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-07-25 01:55:25 +0000
commitea23c3ba4612627ebdb331068f11e02ec6916e75 (patch)
treeb099c2753437a9223b608f349e02d2f47e25e696 /llvm
parent19aac3bd7ee8fba0ce2b4a5f081c43e87bd5caf2 (diff)
downloadbcm5719-llvm-ea23c3ba4612627ebdb331068f11e02ec6916e75.tar.gz
bcm5719-llvm-ea23c3ba4612627ebdb331068f11e02ec6916e75.zip
80 col violation.
llvm-svn: 77041
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 6b0692c7639..2405bd03fd0 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -959,7 +959,8 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
// Build the new ADD / SUB.
- BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg)
+ unsigned Opc = TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri);
+ BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
.addReg(BaseReg, RegState::Kill).addImm(ThisVal)
.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
BaseReg = DestReg;
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