Refine Cell's i64 constant generation code to cover more constants where the

upper and lower 32-bits are the same (in addition to 0 and -1 previously.)

llvm-svn: 47985

2 files changed, 33 insertions, 8 deletions

diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
index de1fff0ccae..6d2a9f3d30b 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -1354,6 +1354,14 @@ SDOperand SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
                               MVT::ValueType ValueType) {
   if (ConstantSDNode *CN = getVecImm(N)) {
     uint64_t Value = CN->getValue();
+    if (ValueType == MVT::i64) {
+      uint64_t UValue = CN->getValue();
+      uint32_t upper = uint32_t(UValue >> 32);
+      uint32_t lower = uint32_t(UValue);
+      if (upper != lower)
+        return SDOperand();
+      Value = Value >> 32;
+    }
     if (Value <= 0x3ffff)
       return DAG.getConstant(Value, ValueType);
   }
@@ -1368,6 +1376,14 @@ SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
                               MVT::ValueType ValueType) {
   if (ConstantSDNode *CN = getVecImm(N)) {
     int64_t Value = CN->getSignExtended();
+    if (ValueType == MVT::i64) {
+      uint64_t UValue = CN->getValue();
+      uint32_t upper = uint32_t(UValue >> 32);
+      uint32_t lower = uint32_t(UValue);
+      if (upper != lower)
+        return SDOperand();
+      Value = Value >> 32;
+    }
     if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) {
       return DAG.getConstant(Value, ValueType);
     }
@@ -1383,6 +1399,14 @@ SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
                               MVT::ValueType ValueType) {
   if (ConstantSDNode *CN = getVecImm(N)) {
     int64_t Value = CN->getSignExtended();
+    if (ValueType == MVT::i64) {
+      uint64_t UValue = CN->getValue();
+      uint32_t upper = uint32_t(UValue >> 32);
+      uint32_t lower = uint32_t(UValue);
+      if (upper != lower)
+        return SDOperand();
+      Value = Value >> 32;
+    }
     if (isS10Constant(Value))
       return DAG.getConstant(Value, ValueType);
   }
@@ -1626,13 +1650,10 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
     uint32_t upper = uint32_t(val >> 32);
     uint32_t lower = uint32_t(val);
 
-    if (val == 0) {
-      SDOperand Zero = DAG.getTargetConstant(0, MVT::i64);
-      return DAG.getNode(ISD::BUILD_VECTOR, VT, Zero, Zero);
-    } else if (val == 0xffffffffffffffffULL) {
-      // For -1, this and has a chance of matching immAllOnesV.
-      SDOperand NegOne = DAG.getTargetConstant(-1, MVT::i64);
-      return DAG.getNode(ISD::BUILD_VECTOR, VT, NegOne, NegOne);
+    if (upper == lower) {
+      // Magic constant that can be matched by IL, ILA, et. al.
+      SDOperand Val = DAG.getTargetConstant(val, MVT::i64);
+      return DAG.getNode(ISD::BUILD_VECTOR, VT, Val, Val);
     } else {
       SDOperand LO32;
       SDOperand HI32;
diff --git a/llvm/test/CodeGen/CellSPU/immed64.ll b/llvm/test/CodeGen/CellSPU/immed64.ll
index f92cdf434bb..7ef3d766bb5 100644
--- a/llvm/test/CodeGen/CellSPU/immed64.ll
+++ b/llvm/test/CodeGen/CellSPU/immed64.ll
@@ -1,6 +1,6 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: grep lqa      %t1.s | count 13
-; RUN: grep il       %t1.s | count 21
+; RUN: grep il       %t1.s | count 22
 ; RUN: grep shufb    %t1.s | count 13
 ; RUN: grep    65520 %t1.s | count 1
 ; RUN: grep    43981 %t1.s | count 1
@@ -57,6 +57,10 @@ define i64 @i64_const_9() {
   ret i64 -1                            ;; IL
 }
 
+define i64 @i64_const_10() {
+  ret i64 281470681808895                ;; IL 65535
+}
+
 ; 0x4005bf0a8b145769 ->
 ;   (ILHU 0x4005 [16389]/IOHL 0xbf0a [48906])
 ;   (ILHU 0x8b14 [35604]/IOHL 0x5769 [22377])