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authorEli Friedman <eli.friedman@gmail.com>2011-07-27 19:43:50 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-07-27 19:43:50 +0000
commite6d1853e7431b3e50b53ce61c673ed9a5b27ea09 (patch)
tree461f8dd0dd9e4cdb348ca06d05df34c22987aca7 /llvm
parent02364191d6f6a2fa680e7238b84d03f298a9cc1b (diff)
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X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any code, and all x86 processors will honor the required semantics.
llvm-svn: 136249
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/X86/X86InstrCompiler.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index adcc747eb4b..17464f380bc 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -532,7 +532,7 @@ def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
let hasSideEffects = 1 in
def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
"#MEMBARRIER",
- [(X86MemBarrier)]>, Requires<[HasSSE2]>;
+ [(X86MemBarrier)]>;
// TODO: Get this to fold the constant into the instruction.
let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in
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