[Hexagon] Properly handle instruction selection of vsplat intrinsics

llvm-svn: 269312

2 files changed, 13 insertions, 2 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index c782638123b..6783ed3b3ad 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -1044,11 +1044,12 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
     return SelectCode(N);
   }
 
-  SDValue const &V = N->getOperand(1);
+  SDValue V = N->getOperand(1);
   SDValue U;
   if (isValueExtension(V, Bits, U)) {
     SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
-      N->getOperand(0), U);
+                                N->getOperand(0), U);
+    ReplaceUses(N, R.getNode());
     return SelectCode(R.getNode());
   }
   return SelectCode(N);
diff --git a/llvm/test/CodeGen/Hexagon/vsplat-isel.ll b/llvm/test/CodeGen/Hexagon/vsplat-isel.ll
new file mode 100644
index 00000000000..9c5e3e17c4e
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/vsplat-isel.ll
@@ -0,0 +1,10 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; CHECK: vsplatb
+
+declare i32 @llvm.hexagon.S2.vsplatrb(i32) #0
+
+define i32 @foo(i8 %x) {
+  %p0 = zext i8 %x to i32
+  %p1 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %p0)
+  ret i32 %p1
+}