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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-12 18:45:52 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-12 18:45:52 +0000 |
| commit | e389dd5d687e13a64301be80e7528e8fa0beaa29 (patch) | |
| tree | 720b8222f78ef69d57380646c63bea8565d06fe4 /llvm | |
| parent | b73c0b041da1f9bd36d79185f5bd51d1befe7fdf (diff) | |
| download | bcm5719-llvm-e389dd5d687e13a64301be80e7528e8fa0beaa29.tar.gz bcm5719-llvm-e389dd5d687e13a64301be80e7528e8fa0beaa29.zip | |
R600: Fix trunc store from i64 to i1
llvm-svn: 203695
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/trunc-store-i1.ll | 30 |
2 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index 8e19e66aaf3..30668f1ed31 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -98,10 +98,16 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); + // XXX: This can be change to Custom, once ExpandVectorStores can // handle 64-bit stores. setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand); + setTruncStoreAction(MVT::i64, MVT::i1, Expand); + setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand); + setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand); + + setOperationAction(ISD::LOAD, MVT::f32, Promote); AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); diff --git a/llvm/test/CodeGen/R600/trunc-store-i1.ll b/llvm/test/CodeGen/R600/trunc-store-i1.ll new file mode 100644 index 00000000000..c3f534ffed5 --- /dev/null +++ b/llvm/test/CodeGen/R600/trunc-store-i1.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s + + +; SI-LABEL: @global_truncstore_i32_to_i1 +; SI: S_LOAD_DWORD [[LOAD:s[0-9]+]], +; SI: V_AND_B32_e64 [[VREG:v[0-9]+]], 1, [[LOAD]], 0, 0, 0, 0 +; SI: BUFFER_STORE_BYTE [[VREG]], +define void @global_truncstore_i32_to_i1(i1 addrspace(1)* %out, i32 %val) nounwind { + %trunc = trunc i32 %val to i1 + store i1 %trunc, i1 addrspace(1)* %out, align 1 + ret void +} + +; SI-LABEL: @global_truncstore_i64_to_i1 +; SI: BUFFER_STORE_BYTE +define void @global_truncstore_i64_to_i1(i1 addrspace(1)* %out, i64 %val) nounwind { + %trunc = trunc i64 %val to i1 + store i1 %trunc, i1 addrspace(1)* %out, align 1 + ret void +} + +; SI-LABEL: @global_truncstore_i16_to_i1 +; SI: S_LOAD_DWORD [[LOAD:s[0-9]+]], +; SI: V_AND_B32_e64 [[VREG:v[0-9]+]], 1, [[LOAD]], 0, 0, 0, 0 +; SI: BUFFER_STORE_BYTE [[VREG]], +define void @global_truncstore_i16_to_i1(i1 addrspace(1)* %out, i16 %val) nounwind { + %trunc = trunc i16 %val to i1 + store i1 %trunc, i1 addrspace(1)* %out, align 1 + ret void +} |
