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| author | Tim Northover <tnorthover@apple.com> | 2016-11-14 22:50:22 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2016-11-14 22:50:22 +0000 |
| commit | e33b175411591f850066cd499f9aa5919c267a86 (patch) | |
| tree | e93b5ef3b60e835efe2e007bb140a13eb3a6a1d3 /llvm | |
| parent | 4f4e522b9721d5c518020b14721427c5681821b0 (diff) | |
| download | bcm5719-llvm-e33b175411591f850066cd499f9aa5919c267a86.tar.gz bcm5719-llvm-e33b175411591f850066cd499f9aa5919c267a86.zip | |
GlobalISel: add tests for G_ZEXT/G_SEXT to types smaller than 32-bits.
Support was accidentally added in r286407, but there were no tests at the time.
llvm-svn: 286903
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index a95829ac73f..a1626f21f6f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -2511,19 +2511,22 @@ regBankSelected: true # CHECK-NEXT: - { id: 1, class: gpr64 } # CHECK-NEXT: - { id: 2, class: gpr32 } # CHECK-NEXT: - { id: 3, class: gpr32 } -# CHECK-NEXT: - { id: 4, class: gpr64 } +# CHECK-NEXT: - { id: 4, class: gpr32 } +# CHECK-NEXT: - { id: 5, class: gpr64 } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } + - { id: 4, class: gpr } # CHECK: body: # CHECK: %0 = COPY %w0 -# CHECK: %4 = SUBREG_TO_REG 0, %0, 15 -# CHECK: %1 = UBFMXri %4, 0, 31 +# CHECK: %5 = SUBREG_TO_REG 0, %0, 15 +# CHECK: %1 = UBFMXri %5, 0, 31 # CHECK: %2 = COPY %w0 # CHECK: %3 = UBFMWri %2, 0, 7 +# CHECK: %4 = UBFMWri %2, 0, 7 body: | bb.0: liveins: %w0 @@ -2532,6 +2535,7 @@ body: | %1(s64) = G_ZEXT %0 %2(s8) = COPY %w0 %3(s32) = G_ZEXT %2 + %4(s16)= G_ZEXT %2 ... --- @@ -2545,19 +2549,22 @@ regBankSelected: true # CHECK-NEXT: - { id: 1, class: gpr64 } # CHECK-NEXT: - { id: 2, class: gpr32 } # CHECK-NEXT: - { id: 3, class: gpr32 } -# CHECK-NEXT: - { id: 4, class: gpr64 } +# CHECK-NEXT: - { id: 4, class: gpr32 } +# CHECK-NEXT: - { id: 5, class: gpr64 } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } + - { id: 4, class: gpr } # CHECK: body: # CHECK: %0 = COPY %w0 -# CHECK: %4 = SUBREG_TO_REG 0, %0, 15 -# CHECK: %1 = SBFMXri %4, 0, 31 +# CHECK: %5 = SUBREG_TO_REG 0, %0, 15 +# CHECK: %1 = SBFMXri %5, 0, 31 # CHECK: %2 = COPY %w0 # CHECK: %3 = SBFMWri %2, 0, 7 +# CHECK: %4 = SBFMWri %2, 0, 7 body: | bb.0: liveins: %w0 @@ -2566,6 +2573,7 @@ body: | %1(s64) = G_SEXT %0 %2(s8) = COPY %w0 %3(s32) = G_SEXT %2 + %4(s16) = G_SEXT %2 ... --- |
