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authorAkira Hatanaka <ahatanaka@mips.com>2011-12-22 01:05:17 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-12-22 01:05:17 +0000
commite2eed9649ebebc1be33f51bdb09b66a85f5f0d3d (patch)
tree39e6a584040f2eb61406448a1645861a6e1b884a /llvm
parent32a756b7ce91ee0debd0274d7fd308d92b774020 (diff)
downloadbcm5719-llvm-e2eed9649ebebc1be33f51bdb09b66a85f5f0d3d.tar.gz
bcm5719-llvm-e2eed9649ebebc1be33f51bdb09b66a85f5f0d3d.zip
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
ELF relocations. Patch by Jack Carter. llvm-svn: 147118
Diffstat (limited to 'llvm')
-rw-r--r--llvm/include/llvm/MC/MCExpr.h1
-rw-r--r--llvm/lib/MC/ELFObjectWriter.cpp9
-rw-r--r--llvm/lib/MC/MCExpr.cpp18
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp3
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h9
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp10
-rw-r--r--llvm/test/MC/Mips/elf-tls.ll36
7 files changed, 85 insertions, 1 deletions
diff --git a/llvm/include/llvm/MC/MCExpr.h b/llvm/include/llvm/MC/MCExpr.h
index e7f5b6a7d5f..195762e64b2 100644
--- a/llvm/include/llvm/MC/MCExpr.h
+++ b/llvm/include/llvm/MC/MCExpr.h
@@ -176,7 +176,6 @@ public:
VK_PPC_GAS_HA16, // symbol@ha
VK_PPC_GAS_LO16, // symbol@l
- VK_Mips_None,
VK_Mips_GPREL,
VK_Mips_GOT_CALL,
VK_Mips_GOT16,
diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp
index ae29753582f..d0b3372b5de 100644
--- a/llvm/lib/MC/ELFObjectWriter.cpp
+++ b/llvm/lib/MC/ELFObjectWriter.cpp
@@ -1474,6 +1474,15 @@ unsigned MipsELFObjectWriter::GetRelocType(const MCValue &Target,
case Mips::fixup_Mips_TPREL_LO:
Type = ELF::R_MIPS_TLS_TPREL_LO16;
break;
+ case Mips::fixup_Mips_TLSLDM:
+ Type = ELF::R_MIPS_TLS_LDM;
+ break;
+ case Mips::fixup_Mips_DTPREL_HI:
+ Type = ELF::R_MIPS_TLS_DTPREL_HI16;
+ break;
+ case Mips::fixup_Mips_DTPREL_LO:
+ Type = ELF::R_MIPS_TLS_DTPREL_LO16;
+ break;
case Mips::fixup_Mips_Branch_PCRel:
case Mips::fixup_Mips_PC16:
Type = ELF::R_MIPS_PC16;
diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
index da297fb1d95..4ebd71a5839 100644
--- a/llvm/lib/MC/MCExpr.cpp
+++ b/llvm/lib/MC/MCExpr.cpp
@@ -200,6 +200,24 @@ StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
case VK_PPC_DARWIN_LO16: return "lo16";
case VK_PPC_GAS_HA16: return "ha";
case VK_PPC_GAS_LO16: return "l";
+ case VK_Mips_GPREL: return "GPREL";
+ case VK_Mips_GOT_CALL: return "GOT_CALL";
+ case VK_Mips_GOT16: return "GOT16";
+ case VK_Mips_GOT: return "GOT";
+ case VK_Mips_ABS_HI: return "ABS_HI";
+ case VK_Mips_ABS_LO: return "ABS_LO";
+ case VK_Mips_TLSGD: return "TLSGD";
+ case VK_Mips_TLSLDM: return "TLSLDM";
+ case VK_Mips_DTPREL_HI: return "DTPREL_HI";
+ case VK_Mips_DTPREL_LO: return "DTPREL_LO";
+ case VK_Mips_GOTTPREL: return "GOTTPREL";
+ case VK_Mips_TPREL_HI: return "TPREL_HI";
+ case VK_Mips_TPREL_LO: return "TPREL_LO";
+ case VK_Mips_GPOFF_HI: return "GPOFF_HI";
+ case VK_Mips_GPOFF_LO: return "GPOFF_LO";
+ case VK_Mips_GOT_DISP: return "GOT_DISP";
+ case VK_Mips_GOT_PAGE: return "GOT_PAGE";
+ case VK_Mips_GOT_OFST: return "GOT_OFST";
}
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
index 699148b22b1..0f57d3cc068 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
@@ -141,6 +141,9 @@ public:
{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
+ { "fixup_Mips_TLSLDM", 0, 16, 0 },
+ { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
+ { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
};
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
index a56c0023150..80026829f98 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
@@ -83,6 +83,15 @@ namespace Mips {
// resulting in - R_MIPS_TLS_TPREL_LO16.
fixup_Mips_TPREL_LO,
+ // resulting in - R_MIPS_TLS_LDM.
+ fixup_Mips_TLSLDM,
+
+ // resulting in - R_MIPS_TLS_DTPREL_HI16.
+ fixup_Mips_DTPREL_HI,
+
+ // resulting in - R_MIPS_TLS_DTPREL_LO16.
+ fixup_Mips_DTPREL_LO,
+
// PC relative branch fixup resulting in - R_MIPS_PC16
fixup_Mips_Branch_PCRel,
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 463dcfe55dc..53cfd98d379 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -187,6 +187,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
if (Kind == MCExpr::SymbolRef) {
Mips::Fixups FixupKind;
+
switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
case MCSymbolRefExpr::VK_Mips_GPREL:
FixupKind = Mips::fixup_Mips_GPREL16;
@@ -209,6 +210,15 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
case MCSymbolRefExpr::VK_Mips_TLSGD:
FixupKind = Mips::fixup_Mips_TLSGD;
break;
+ case MCSymbolRefExpr::VK_Mips_TLSLDM:
+ FixupKind = Mips::fixup_Mips_TLSLDM;
+ break;
+ case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
+ FixupKind = Mips::fixup_Mips_DTPREL_HI;
+ break;
+ case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
+ FixupKind = Mips::fixup_Mips_DTPREL_LO;
+ break;
case MCSymbolRefExpr::VK_Mips_GOTTPREL:
FixupKind = Mips::fixup_Mips_GOTTPREL;
break;
diff --git a/llvm/test/MC/Mips/elf-tls.ll b/llvm/test/MC/Mips/elf-tls.ll
new file mode 100644
index 00000000000..b4183b83577
--- /dev/null
+++ b/llvm/test/MC/Mips/elf-tls.ll
@@ -0,0 +1,36 @@
+; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s
+
+; Check that the appropriate relocations were created.
+
+; CHECK: ('r_type', 0x2b)
+; CHECK: ('r_type', 0x2c)
+; CHECK: ('r_type', 0x2d)
+
+@t1 = thread_local global i32 0, align 4
+
+define i32 @f1() nounwind {
+entry:
+ %tmp = load i32* @t1, align 4
+ ret i32 %tmp
+
+}
+
+
+@t2 = external thread_local global i32
+
+define i32 @f2() nounwind {
+entry:
+ %tmp = load i32* @t2, align 4
+ ret i32 %tmp
+
+}
+
+@f3.i = internal thread_local unnamed_addr global i32 1, align 4
+
+define i32 @f3() nounwind {
+entry:
+ %0 = load i32* @f3.i, align 4
+ %inc = add nsw i32 %0, 1
+ store i32 %inc, i32* @f3.i, align 4
+ ret i32 %inc
+}
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