Fold preceding / trailing base inc / dec into the single load / store as well.

llvm-svn: 72756

2 files changed, 21 insertions, 2 deletions

diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 047552f627d..108c6dd4d6b 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -697,7 +697,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
         // LDM/STM ops.
         for (unsigned i = 0, e = MBBII.size(); i < e; ++i)
           if (mergeBaseUpdateLSMultiple(MBB, MBBII[i], Advance, MBBI))
-            NumMerges++;
+            ++NumMerges;
         NumMerges += MBBII.size();
 
         // Try folding preceeding/trailing base inc/dec into those load/store
@@ -705,10 +705,17 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
         for (unsigned i = 0; i != NumMemOps; ++i)
           if (!MemOps[i].Merged)
             if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
-              NumMerges++;
+              ++NumMerges;
 
         // RS may be pointing to an instruction that's deleted. 
         RS->skipTo(prior(MBBI));
+      } else if (NumMemOps == 1) {
+        // Try folding preceeding/trailing base inc/dec into the single
+        // load/store.
+        if (mergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) {
+          ++NumMerges;
+          RS->skipTo(prior(MBBI));
+        }
       }
 
       CurrBase = 0;
diff --git a/llvm/test/CodeGen/ARM/str_pre-2.ll b/llvm/test/CodeGen/ARM/str_pre-2.ll
new file mode 100644
index 00000000000..e9f194574e4
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/str_pre-2.ll
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {str.*\\!}
+; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4}
+
+@b = external global i64*
+
+define i64 @t(i64 %a) nounwind readonly {
+entry:
+	%0 = load i64** @b, align 4
+	%1 = load i64* %0, align 4
+	%2 = mul i64 %1, %a
+	ret i64 %2
+}