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| author | Craig Topper <craig.topper@intel.com> | 2018-08-23 17:45:53 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-08-23 17:45:53 +0000 |
| commit | dfa176e813e6ac69b9fc8530ef25637be7a0ba15 (patch) | |
| tree | bd8182d90e42872748210e109ec143f417da3262 /llvm | |
| parent | ab038025a50c79a89edb5832b163e8c729ceb703 (diff) | |
| download | bcm5719-llvm-dfa176e813e6ac69b9fc8530ef25637be7a0ba15.tar.gz bcm5719-llvm-dfa176e813e6ac69b9fc8530ef25637be7a0ba15.zip | |
[ValueTracking] Fix assert message and add test case for r340546 and PR38677.
The bug was already fixed. This just adds a test case for it.
llvm-svn: 340556
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Analysis/ValueTracking.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/pr38677.ll | 33 |
2 files changed, 34 insertions, 1 deletions
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index d2844d80c51..a207a5064db 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2215,7 +2215,7 @@ static bool isSignedMinMaxClamp(const Value *Select, const Value *&In, const APInt *&CLow, const APInt *&CHigh) { assert(isa<Operator>(Select) && cast<Operator>(Select)->getOpcode() == Instruction::Select && - "Input should be a SelectInst!"); + "Input should be a Select!"); const Value *LHS, *RHS, *LHS2, *RHS2; SelectPatternFlavor SPF = matchSelectPattern(Select, LHS, RHS).Flavor; diff --git a/llvm/test/Transforms/InstCombine/pr38677.ll b/llvm/test/Transforms/InstCombine/pr38677.ll new file mode 100644 index 00000000000..e5c6178105d --- /dev/null +++ b/llvm/test/Transforms/InstCombine/pr38677.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +;RUN: opt -instcombine -S %s | FileCheck %s + +@A = extern_weak global i32, align 4 +@B = extern_weak global i32, align 4 + +define i32 @foo(i1 %which) { +; CHECK-LABEL: @foo( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 true, label [[FINAL:%.*]], label [[DELAY:%.*]] +; CHECK: delay: +; CHECK-NEXT: br label [[FINAL]] +; CHECK: final: +; CHECK-NEXT: [[USE2:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ select (i1 icmp eq (i32* @A, i32* @B), i32 2, i32 1), [[DELAY]] ] +; CHECK-NEXT: [[B7:%.*]] = mul i32 [[USE2]], 2147483647 +; CHECK-NEXT: [[C3:%.*]] = icmp eq i32 [[B7]], 0 +; CHECK-NEXT: store i1 [[C3]], i1* undef, align 1 +; CHECK-NEXT: ret i32 [[USE2]] +; +entry: + br i1 true, label %final, label %delay + +delay: ; preds = %entry + br label %final + +final: ; preds = %delay, %entry + %use2 = phi i1 [ false, %entry ], [ icmp eq (i32* @A, i32* @B), %delay ] + %value = select i1 %use2, i32 2, i32 1 + %B7 = mul i32 %value, 2147483647 + %C3 = icmp ule i32 %B7, 0 + store i1 %C3, i1* undef + ret i32 %value +} |
