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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 01:56:38 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 01:56:38 +0000 |
| commit | de8231eada12167cc2122ba35ab9b6d8660cdc4c (patch) | |
| tree | bf673865e0938b8b1c89d427bec173f0bba66986 /llvm | |
| parent | 453807fffea4182f7974318e460aaad584c5a831 (diff) | |
| download | bcm5719-llvm-de8231eada12167cc2122ba35ab9b6d8660cdc4c.tar.gz bcm5719-llvm-de8231eada12167cc2122ba35ab9b6d8660cdc4c.zip | |
MIPS DSP: add bitcast patterns between vectors and int.
No test cases. These patterns will get tested along with dsp intrinsics.
llvm-svn: 164746
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td index 556cf6bc500..b9f40efbd1d 100644 --- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td @@ -23,6 +23,16 @@ def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : Pat<pattern, result>, Requires<[pred]>; +class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, + RegisterClass SrcRC> : + DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), + (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; + +def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>; +def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>; +def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>; +def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>; + def : DSPPat<(v2i16 (load addr:$a)), (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; def : DSPPat<(v4i8 (load addr:$a)), |
