diff options
| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-18 14:09:07 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-18 14:09:07 +0000 |
| commit | d5c6a63a500f903c1e2430e27a3ed9fbb62f935a (patch) | |
| tree | c6f9f8de5dc92ec407176bf55d5749f320e6871d /llvm | |
| parent | 41f1fcd80e5e0ec9c97bec086010cfb5ae5883a0 (diff) | |
| download | bcm5719-llvm-d5c6a63a500f903c1e2430e27a3ed9fbb62f935a.tar.gz bcm5719-llvm-d5c6a63a500f903c1e2430e27a3ed9fbb62f935a.zip | |
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
llvm-svn: 155002
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 20 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt | 18 |
2 files changed, 33 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 7b0a3ac42ab..807577e7696 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -4646,22 +4646,32 @@ def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; // // Move to ARM core register from Special Register -def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, +def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> { bits<4> Rd; let Inst{23-16} = 0b00001111; + let Unpredictable{19-17} = 0b111; + let Inst{15-12} = Rd; - let Inst{7-4} = 0b0000; + + let Inst{11-0} = 0b000000000000; + let Unpredictable{11-0} = 0b110100001111; } -def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>; +def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, Requires<[IsARM]>; -def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, +// The MRSsys instruction is the MRS instruction from the ARM ARM, +// section B9.3.9, with the R bit set to 1. +def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> { bits<4> Rd; let Inst{23-16} = 0b01001111; + let Unpredictable{19-16} = 0b1111; + let Inst{15-12} = Rd; - let Inst{7-4} = 0b0000; + + let Inst{11-0} = 0b000000000000; + let Unpredictable{11-0} = 0b110100001111; } // Move from ARM core register to Special Register diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt new file mode 100644 index 00000000000..3e472cdbfb1 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: 0x00 0xf0 0x0f 0x01 +0x00 0xf0 0x0f 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x00 0xf0 0x4f 0x01 +0x00 0xf0 0x4f 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x0f 0x0d 0x01 0x01 +0x0f 0x0d 0x01 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x0f 0x0d 0x40 0x01 +0x0f 0x0d 0x40 0x01 + |
