[X86] EltsFromConsecutiveLoads - early out for non-byte sized memory (PR42909)

Don't attempt to merge loads for types that aren't modulo 8-bits.

llvm-svn: 368165

2 files changed, 24 insertions, 0 deletions

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 3a2fca7de71..d85d6bc2020 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7631,6 +7631,9 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
                                         const SDLoc &DL, SelectionDAG &DAG,
                                         const X86Subtarget &Subtarget,
                                         bool isAfterLegalize) {
+  if ((VT.getScalarSizeInBits() % 8) != 0)
+    return SDValue();
+
   unsigned NumElems = Elts.size();
 
   int LastLoadedElt = -1;
diff --git a/llvm/test/CodeGen/X86/pr42909.ll b/llvm/test/CodeGen/X86/pr42909.ll
new file mode 100644
index 00000000000..afa9fe9d55d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr42909.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 -x86-experimental-vector-widening-legalization=1 | FileCheck %s
+
+define void @autogen_SD31033(i16* %a0) {
+; CHECK-LABEL: autogen_SD31033:
+; CHECK:       # %bb.0: # %BB
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_1: # %CF
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    jmp .LBB0_1
+BB:
+  %L5 = load i16, i16* %a0
+  %I8 = insertelement <4 x i16> zeroinitializer, i16 %L5, i32 1
+  %Tr = trunc <4 x i16> %I8 to <4 x i1>
+  %Shuff28 = shufflevector <4 x i1> zeroinitializer, <4 x i1> %Tr, <4 x i32> <i32 undef, i32 3, i32 5, i32 undef>
+  br label %CF
+
+CF:                                               ; preds = %CF, %BB
+  %E42 = extractelement <4 x i1> %Shuff28, i32 3
+  br label %CF
+}