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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-05-03 15:05:13 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-05-03 15:05:13 +0000 |
| commit | d2752708a3a0d598127422339c09b866410b6ff1 (patch) | |
| tree | 96b5aaa94b419761d437385022ca05a9d7bd8eae /llvm | |
| parent | 43d7e1cbffd668e188f19784ca876032255626e4 (diff) | |
| download | bcm5719-llvm-d2752708a3a0d598127422339c09b866410b6ff1.tar.gz bcm5719-llvm-d2752708a3a0d598127422339c09b866410b6ff1.zip | |
[X86][SSE] Added target shuffle combine to MOVQ
llvm-svn: 268391
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll | 4 |
2 files changed, 18 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9dbf5d642b6..cc1bf05c436 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -24134,6 +24134,22 @@ static bool combineX86ShuffleChain(SDValue Input, SDValue Root, return true; } + // Match a 128-bit integer vector against a VZEXT_MOVL (MOVQ) instruction. + if (!FloatDomain && VT.is128BitVector() && + Mask.size() == 2 && Mask[0] == 0 && Mask[1] < 0) { + unsigned Shuffle = X86ISD::VZEXT_MOVL; + MVT ShuffleVT = MVT::v2i64; + if (Depth == 1 && Root->getOpcode() == Shuffle) + return false; // Nothing to do! + Res = DAG.getBitcast(ShuffleVT, Input); + DCI.AddToWorklist(Res.getNode()); + Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res, Res); + DCI.AddToWorklist(Res.getNode()); + DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Res), + /*AddTo*/ true); + return true; + } + // Attempt to blend with zero. if (VT.getVectorNumElements() <= 8 && ((Subtarget.hasSSE41() && VT.is128BitVector()) || diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll index b98141377e0..034811b576d 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll @@ -28,12 +28,12 @@ define <16 x i8> @combine_vpshufb_zero(<16 x i8> %a0) { define <16 x i8> @combine_vpshufb_movq(<16 x i8> %a0) { ; SSE-LABEL: combine_vpshufb_movq: ; SSE: # BB#0: -; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero +; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vpshufb_movq: ; AVX: # BB#0: -; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero +; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX-NEXT: retq %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 128, i8 1, i8 128, i8 2, i8 128, i8 3, i8 128, i8 4, i8 128, i8 5, i8 128, i8 6, i8 128, i8 7, i8 128>) %res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 2, i8 4, i8 6, i8 8, i8 10, i8 12, i8 14, i8 1, i8 3, i8 5, i8 7, i8 9, i8 11, i8 13, i8 15>) |
