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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-22 18:13:31 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-22 18:13:31 +0000 |
| commit | d1f8bde10f0c7bb0cab5ebf6171909fa808ac2fc (patch) | |
| tree | 1871650d1bfcd7ff69c7065212502d4a0b8986ce /llvm | |
| parent | bc9d8418782a0ac51c17b4142d7dc426923bbbb6 (diff) | |
| download | bcm5719-llvm-d1f8bde10f0c7bb0cab5ebf6171909fa808ac2fc.tar.gz bcm5719-llvm-d1f8bde10f0c7bb0cab5ebf6171909fa808ac2fc.zip | |
ARM assembly parsing and encoding for SMC instruction.
llvm-svn: 135782
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/basic-arm-instructions.s | 9 |
3 files changed, 12 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 7b675c85327..fb822355cd6 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1742,8 +1742,8 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { // Secure Monitor Call is a system instruction -- for disassembly only -def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", - [/* For disassembly only; pattern left blank */]> { +def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", + []> { bits<4> opt; let Inst{23-4} = 0b01100000000000000111; let Inst{3-0} = opt; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 6241b31da60..287c2d94d28 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3170,7 +3170,7 @@ def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> { // Secure Monitor Call is a system instruction -- for disassembly only // Option = Inst{19-16} -def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", +def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11110; let Inst{26-20} = 0b1111111; diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s index 42a60a463fa..dcaf602780b 100644 --- a/llvm/test/MC/ARM/basic-arm-instructions.s +++ b/llvm/test/MC/ARM/basic-arm-instructions.s @@ -1359,6 +1359,15 @@ _func: @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6] @ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6] +@------------------------------------------------------------------------------ +@ SMC +@------------------------------------------------------------------------------ + smc #0xf + smceq #0 + +@ CHECK: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1] +@ CHECK: smceq #0 @ encoding: [0x70,0x00,0x60,0x01] + @------------------------------------------------------------------------------ @ STM* |
