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| author | Anshuman Dasgupta <adasgupt@codeaurora.org> | 2013-02-21 19:39:40 +0000 |
|---|---|---|
| committer | Anshuman Dasgupta <adasgupt@codeaurora.org> | 2013-02-21 19:39:40 +0000 |
| commit | d062c704446ada1bd93d378cd4f09c03ccc745f8 (patch) | |
| tree | e8d6d5546f22333dc28e833af7608899d2c974c0 /llvm | |
| parent | 2ff4dc0ff2e9b72d70ccd54e9552d869f33d4b4b (diff) | |
| download | bcm5719-llvm-d062c704446ada1bd93d378cd4f09c03ccc745f8.tar.gz bcm5719-llvm-d062c704446ada1bd93d378cd4f09c03ccc745f8.zip | |
Hexagon: Expand cttz, ctlz, and ctpop for now.
llvm-svn: 175783
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll | 34 |
2 files changed, 39 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 99a5db35e13..fac931a4bde 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1366,10 +1366,15 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine setOperationAction(ISD::FSINCOS, MVT::f64, Expand); setOperationAction(ISD::FSINCOS, MVT::f32, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); setOperationAction(ISD::CTTZ , MVT::i32, Expand); + setOperationAction(ISD::CTTZ , MVT::i64, Expand); setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); setOperationAction(ISD::CTLZ , MVT::i32, Expand); + setOperationAction(ISD::CTLZ , MVT::i64, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTR , MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i32, Expand); diff --git a/llvm/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll new file mode 100644 index 00000000000..e942f8d0c5d --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll @@ -0,0 +1,34 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s + +; CHECK: r{{[0-9]+}}:{{[0-9]+}} |= lsr(r{{[0-9]+}}:{{[0-9]+}}, #4) +; CHECK: r{{[0-9]+}}:{{[0-9]+}} &= lsr(r{{[0-9]+}}:{{[0-9]+}}, #2) +; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4) + +define i32 @foo(i64 %a, i32 %b) nounwind { +entry: + %tmp0 = tail call i64 @llvm.ctlz.i64( i64 %a, i1 true ) + %tmp1 = tail call i64 @llvm.cttz.i64( i64 %a, i1 true ) + %tmp2 = tail call i32 @llvm.ctlz.i32( i32 %b, i1 true ) + %tmp3 = tail call i32 @llvm.cttz.i32( i32 %b, i1 true ) + %tmp4 = tail call i64 @llvm.ctpop.i64( i64 %a ) + %tmp5 = tail call i32 @llvm.ctpop.i32( i32 %b ) + + + %tmp6 = trunc i64 %tmp0 to i32 + %tmp7 = trunc i64 %tmp1 to i32 + %tmp8 = trunc i64 %tmp4 to i32 + %tmp9 = add i32 %tmp6, %tmp7 + %tmp10 = add i32 %tmp9, %tmp8 + %tmp11 = add i32 %tmp10, %tmp2 + %tmp12 = add i32 %tmp11, %tmp3 + %tmp13 = add i32 %tmp12, %tmp5 + + ret i32 %tmp13 +} + +declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone +declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone +declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone +declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone +declare i64 @llvm.ctpop.i64(i64) nounwind readnone +declare i32 @llvm.ctpop.i32(i32) nounwind readnone |
