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| author | Craig Topper <craig.topper@intel.com> | 2018-11-18 08:30:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-11-18 08:30:09 +0000 |
| commit | cd94a7c22791a70c363c6177ec1746167e0d5426 (patch) | |
| tree | e2a9cbdba421bd1cd4486bfc29b6ea1e5d718d63 /llvm | |
| parent | b03f80a21c44fae7afe52f3f0e17fbf2d46b4318 (diff) | |
| download | bcm5719-llvm-cd94a7c22791a70c363c6177ec1746167e0d5426.tar.gz bcm5719-llvm-cd94a7c22791a70c363c6177ec1746167e0d5426.zip | |
[X86] Add -x86-experimental-vector-widening-legalization check to combineSelect and combineSetCC to cover vXi16/vXi8 promotion without BWI.
I don't yet have any test cases for this, but its the right thing to do based on log file inspection.
llvm-svn: 347151
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6fbdeb2ef47..7eae08e54c2 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -33650,7 +33650,8 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, // Since SKX these selects have a proper lowering. if (Subtarget.hasAVX512() && !Subtarget.hasBWI() && CondVT.isVector() && CondVT.getVectorElementType() == MVT::i1 && - VT.getVectorNumElements() > 4 && + (ExperimentalVectorWideningLegalization || + VT.getVectorNumElements() > 4) && (VT.getVectorElementType() == MVT::i8 || VT.getVectorElementType() == MVT::i16)) { Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond); @@ -39186,7 +39187,9 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG, // NOTE: The element count check is to ignore operand types that need to // go through type promotion to a 128-bit vector. if (Subtarget.hasAVX512() && !Subtarget.hasBWI() && VT.isVector() && - VT.getVectorElementType() == MVT::i1 && VT.getVectorNumElements() > 4 && + VT.getVectorElementType() == MVT::i1 && + (ExperimentalVectorWideningLegalization || + VT.getVectorNumElements() > 4) && (OpVT.getVectorElementType() == MVT::i8 || OpVT.getVectorElementType() == MVT::i16)) { SDValue Setcc = DAG.getNode(ISD::SETCC, DL, OpVT, LHS, RHS, |
