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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-08 21:04:05 +0000 | 
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-08 21:04:05 +0000 | 
| commit | cb1b0b7130387edaeab5bef07ef372b7908af4d5 (patch) | |
| tree | eb12fb4722de1c355c6314f4f2456b88b1d7e6f1 /llvm | |
| parent | 576e96e0dc8ab560f79b1096f0a942cd0fa1dcb5 (diff) | |
| download | bcm5719-llvm-cb1b0b7130387edaeab5bef07ef372b7908af4d5.tar.gz bcm5719-llvm-cb1b0b7130387edaeab5bef07ef372b7908af4d5.zip | |
Shuffle productions around a bit.
No functional change.
llvm-svn: 134737
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 42 | 
1 files changed, 21 insertions, 21 deletions
| diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index c3fb83db47c..10038c88f1b 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -361,27 +361,6 @@ def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,  //  Control Flow Instructions.  // -let isReturn = 1, isTerminator = 1, isBarrier = 1 in { -  def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", -                   [(ARMretflag)]>, -                T1Special<{1,1,0,?}> { -    // A6.2.3 & A8.6.25 -    let Inst{6-3} = 0b1110; // Rm = lr -    let Inst{2-0} = 0b000; -  } - -  // Alternative return instruction used by vararg functions. -  def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm), -                          IIC_Br, "bx\t$Rm", -                          []>, -                       T1Special<{1,1,0,?}> { -    // A6.2.3 & A8.6.25 -    bits<4> Rm; -    let Inst{6-3} = Rm; -    let Inst{2-0} = 0b000; -  } -} -  // Indirect branches  let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {    def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, @@ -405,6 +384,27 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {    }  } +let isReturn = 1, isTerminator = 1, isBarrier = 1 in { +  def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", +                   [(ARMretflag)]>, +                T1Special<{1,1,0,?}> { +    // A6.2.3 & A8.6.25 +    let Inst{6-3} = 0b1110; // Rm = lr +    let Inst{2-0} = 0b000; +  } + +  // Alternative return instruction used by vararg functions. +  def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm), +                          IIC_Br, "bx\t$Rm", +                          []>, +                       T1Special<{1,1,0,?}> { +    // A6.2.3 & A8.6.25 +    bits<4> Rm; +    let Inst{6-3} = Rm; +    let Inst{2-0} = 0b000; +  } +} +  // All calls clobber the non-callee saved registers. SP is marked as a use to  // prevent stack-pointer assignments that appear immediately before calls from  // potentially appearing dead. | 

