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authorEvan Cheng <evan.cheng@apple.com>2010-05-14 00:21:45 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-05-14 00:21:45 +0000
commitca21cc8b1309c01422f7ba4baa090de0bf96be59 (patch)
treeb9f462de85a7c41ccbdd2e6c02b86fbabf467998 /llvm
parent68c235bd4db9cec4520ae6711670262e075cab1f (diff)
downloadbcm5719-llvm-ca21cc8b1309c01422f7ba4baa090de0bf96be59.tar.gz
bcm5719-llvm-ca21cc8b1309c01422f7ba4baa090de0bf96be59.zip
Fix comments.
llvm-svn: 103749
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 294486c99f7..edb6c9cfe84 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -968,7 +968,7 @@ SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
VT, SDValue(Pair, 0), V1, SubReg1);
}
-/// PairDRegs - Form a quad register pair from a pair of Q registers.
+/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
///
SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
DebugLoc dl = V0.getNode()->getDebugLoc();
@@ -978,7 +978,7 @@ SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
}
-/// QuadDRegs - Form a octo register from a quad of D registers.
+/// QuadDRegs - Form 4 consecutive D registers.
///
SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
SDValue V2, SDValue V3) {
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