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| author | David L Kreitzer <david.l.kreitzer@intel.com> | 2016-05-03 20:16:08 +0000 |
|---|---|---|
| committer | David L Kreitzer <david.l.kreitzer@intel.com> | 2016-05-03 20:16:08 +0000 |
| commit | c9fbf1018a7430f9bb7b0a46b148b93a0dab50ad (patch) | |
| tree | ae081fb9320f4c7ddd48776f4fa75689260268e1 /llvm | |
| parent | 4e05b82cc495a15dac4ce05ad1d2648ba3c739bc (diff) | |
| download | bcm5719-llvm-c9fbf1018a7430f9bb7b0a46b148b93a0dab50ad.tar.gz bcm5719-llvm-c9fbf1018a7430f9bb7b0a46b148b93a0dab50ad.zip | |
Add an address space for the X86 SS segment.
Patch by Michael LeMay (michael.lemay@intel.com)
Differential Revision: http://reviews.llvm.org/D17093
llvm-svn: 268431
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/docs/CodeGenerator.rst | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 10 |
2 files changed, 11 insertions, 5 deletions
diff --git a/llvm/docs/CodeGenerator.rst b/llvm/docs/CodeGenerator.rst index 347a372d80e..a84645da7ce 100644 --- a/llvm/docs/CodeGenerator.rst +++ b/llvm/docs/CodeGenerator.rst @@ -2197,9 +2197,9 @@ prefix byte on an instruction causes the instruction's memory access to go to the specified segment. LLVM address space 0 is the default address space, which includes the stack, and any unqualified memory accesses in a program. Address spaces 1-255 are currently reserved for user-defined code. The GS-segment is -represented by address space 256, while the FS-segment is represented by address -space 257. Other x86 segments have yet to be allocated address space -numbers. +represented by address space 256, the FS-segment is represented by address space +257, and the SS-segment is represented by address space 258. Other x86 segments +have yet to be allocated address space numbers. While these address spaces may seem similar to TLS via the ``thread_local`` keyword, and often use the same underlying hardware, there are some fundamental diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 54c47011265..4fa7a0fccc0 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -727,6 +727,8 @@ bool X86DAGToDAGISel::matchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){ case 257: AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); return false; + // Address space 258 is not handled here, because it is not used to + // address TLS areas. } return true; @@ -1424,11 +1426,13 @@ bool X86DAGToDAGISel::selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base, return false; X86ISelAddressMode AM; unsigned AddrSpace = Mgs->getPointerInfo().getAddrSpace(); - // AddrSpace 256 -> GS, 257 -> FS. + // AddrSpace 256 -> GS, 257 -> FS, 258 -> SS. if (AddrSpace == 256) AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); if (AddrSpace == 257) AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); + if (AddrSpace == 258) + AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16); SDLoc DL(N); Base = Mgs->getBasePtr(); @@ -1473,11 +1477,13 @@ bool X86DAGToDAGISel::selectAddr(SDNode *Parent, SDValue N, SDValue &Base, Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp unsigned AddrSpace = cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace(); - // AddrSpace 256 -> GS, 257 -> FS. + // AddrSpace 256 -> GS, 257 -> FS, 258 -> SS. if (AddrSpace == 256) AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); if (AddrSpace == 257) AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); + if (AddrSpace == 258) + AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16); } if (matchAddress(N, AM)) |
