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authorOwen Anderson <resistor@mac.com>2011-03-29 17:42:25 +0000
committerOwen Anderson <resistor@mac.com>2011-03-29 17:42:25 +0000
commitc48981f7293d1477b605be7ec4ab2c851d17e4ec (patch)
treede7bab5cd07785363e2fac4a307dec840ef300d1 /llvm
parent1c6b6814139807755f0613959823c9f51a2d367c (diff)
downloadbcm5719-llvm-c48981f7293d1477b605be7ec4ab2c851d17e4ec.tar.gz
bcm5719-llvm-c48981f7293d1477b605be7ec4ab2c851d17e4ec.zip
Add safety check that didn't show up in testing.
llvm-svn: 128467
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index af731166265..0dab835f7c8 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -350,6 +350,7 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
Opcode == ARM::VLDRD);
Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
+ if (!Opcode) return false;
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
.addReg(Base, getKillRegState(BaseKill))
.addImm(Pred).addReg(PredReg);
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