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authorPetr Hosek <phosek@chromium.org>2017-04-07 20:41:58 +0000
committerPetr Hosek <phosek@chromium.org>2017-04-07 20:41:58 +0000
commitc3a9e6db3811c0a459137430c121210e83541c93 (patch)
treead47c1a52671903fc342d2e3a725ed7239ab6aec /llvm
parentdf82d93562591fd948d15669703610b62becaffe (diff)
downloadbcm5719-llvm-c3a9e6db3811c0a459137430c121210e83541c93.tar.gz
bcm5719-llvm-c3a9e6db3811c0a459137430c121210e83541c93.zip
[AArch64] Allow global register asm("x18") or asm("w18") under -ffixed-x18
When using -ffixed-x18, the x18 (or w18) register can safely be used with the "global register variable" GCC extension, but the backend fails to recognize it. Patch by Roland McGrath. Differential Revision: https://reviews.llvm.org/D31793 llvm-svn: 299799
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelLowering.cpp5
-rw-r--r--llvm/test/CodeGen/AArch64/aarch64-named-reg-w18.ll14
-rw-r--r--llvm/test/CodeGen/AArch64/aarch64-named-reg-x18.ll14
3 files changed, 33 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ea184d55e44..7dd62f78a8f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4510,7 +4510,12 @@ unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const {
unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("sp", AArch64::SP)
+ .Case("x18", AArch64::X18)
+ .Case("w18", AArch64::W18)
.Default(0);
+ if ((Reg == AArch64::X18 || Reg == AArch64::W18) &&
+ !Subtarget->isX18Reserved())
+ Reg = 0;
if (Reg)
return Reg;
report_fatal_error(Twine("Invalid register name \""
diff --git a/llvm/test/CodeGen/AArch64/aarch64-named-reg-w18.ll b/llvm/test/CodeGen/AArch64/aarch64-named-reg-w18.ll
new file mode 100644
index 00000000000..341c7683dba
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-named-reg-w18.ll
@@ -0,0 +1,14 @@
+; RUN: not llc -mtriple=aarch64-fuchsia -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR
+; RUN: llc -mtriple=aarch64-fuchsia -mattr=+reserve-x18 -o - %s
+
+define void @set_w18(i32 %x) {
+entry:
+; FIXME: Include an allocatable-specific error message
+; ERROR: Invalid register name "w18".
+ tail call void @llvm.write_register.i32(metadata !0, i32 %x)
+ ret void
+}
+
+declare void @llvm.write_register.i32(metadata, i32) nounwind
+
+!0 = !{!"w18"}
diff --git a/llvm/test/CodeGen/AArch64/aarch64-named-reg-x18.ll b/llvm/test/CodeGen/AArch64/aarch64-named-reg-x18.ll
new file mode 100644
index 00000000000..eed852710ba
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-named-reg-x18.ll
@@ -0,0 +1,14 @@
+; RUN: not llc -mtriple=aarch64-fuchsia -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR
+; RUN: llc -mtriple=aarch64-fuchsia -mattr=+reserve-x18 -o - %s
+
+define void @set_x18(i64 %x) {
+entry:
+; FIXME: Include an allocatable-specific error message
+; ERROR: Invalid register name "x18".
+ tail call void @llvm.write_register.i64(metadata !0, i64 %x)
+ ret void
+}
+
+declare void @llvm.write_register.i64(metadata, i64) nounwind
+
+!0 = !{!"x18"}
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