[RegisterBankInfo] Change the API for the verify methods.

Return bool instead of void so that it is natural to put the calls into
asserts.

llvm-svn: 267033

6 files changed, 42 insertions, 16 deletions

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
index ef468ff4b5f..e886382fd8e 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
@@ -61,7 +61,11 @@ public:
 
   /// Check if this register bank is valid. In other words,
   /// if it has been properly constructed.
-  void verify(const TargetRegisterInfo &TRI) const;
+  ///
+  /// \note This method does not check anything when assertions are disabled.
+  ///
+  /// \return True is the check was successful.
+  bool verify(const TargetRegisterInfo &TRI) const;
 
   /// Check whether this register bank covers \p RC.
   /// In other words, check if this register bank fully covers
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
index b0edd8494f2..b640637cdee 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -73,7 +73,11 @@ public:
     /// Check that the Mask is compatible with the RegBank.
     /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
     /// there is no way this mapping is valid.
-    void verify() const;
+    ///
+    /// \note This method does not check anything when assertions are disabled.
+    ///
+    /// \return True is the check was successful.
+    bool verify() const;
   };
 
   /// Helper struct that represents how a value is mapped through
@@ -83,7 +87,10 @@ public:
     SmallVector<PartialMapping, 2> BreakDown;
 
     /// Verify that this mapping makes sense for a value of \p ExpectedBitWidth.
-    void verify(unsigned ExpectedBitWidth) const;
+    /// \note This method does not check anything when assertions are disabled.
+    ///
+    /// \return True is the check was successful.
+    bool verify(unsigned ExpectedBitWidth) const;
 
     /// Print this on dbgs() stream.
     void dump() const;
@@ -163,7 +170,11 @@ public:
 
     /// Verifiy that this mapping makes sense for \p MI.
     /// \pre \p MI must be connected to a MachineFunction.
-    void verify(const MachineInstr &MI) const;
+    ///
+    /// \note This method does not check anything when assertions are disabled.
+    ///
+    /// \return True is the check was successful.
+    bool verify(const MachineInstr &MI) const;
 
     /// Print this on dbgs() stream.
     void dump() const;
@@ -401,7 +412,13 @@ public:
   /// \post !returnedVal.empty().
   InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;
 
-  void verify(const TargetRegisterInfo &TRI) const;
+  /// Check that information hold by this instance make sense for the
+  /// given \p TRI.
+  ///
+  /// \note This method does not check anything when assertions are disabled.
+  ///
+  /// \return True is the check was successful.
+  bool verify(const TargetRegisterInfo &TRI) const;
 };
 
 inline raw_ostream &
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index 4504d18b33e..8a6e1cb3623 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -167,7 +167,7 @@ void RegBankSelect::assignInstr(MachineInstr &MI) {
   const RegisterBankInfo::InstructionMapping DefaultMapping =
       RBI->getInstrMapping(MI);
   // Make sure the mapping is valid for MI.
-  DefaultMapping.verify(MI);
+  assert(DefaultMapping.verify(MI) && "Invalid instruction mapping");
 
   DEBUG(dbgs() << "Mapping: " << DefaultMapping << '\n');
 
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
index aae8148bcbb..01ee4d77a3a 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
@@ -22,7 +22,7 @@ const unsigned RegisterBank::InvalidID = UINT_MAX;
 
 RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Size(0) {}
 
-void RegisterBank::verify(const TargetRegisterInfo &TRI) const {
+bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
   assert(isValid() && "Invalid register bank");
   assert(ContainedRegClasses.size() == TRI.getNumRegClasses() &&
          "TRI does not match the initialization process?");
@@ -50,6 +50,7 @@ void RegisterBank::verify(const TargetRegisterInfo &TRI) const {
       assert(covers(SubRC) && "Not all subclasses are covered");
     }
   }
+  return true;
 }
 
 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 9cd6af0ac85..032908f4479 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -67,14 +67,15 @@ RegisterBankInfo::RegisterBankInfo(unsigned NumRegBanks)
   RegBanks.reset(new RegisterBank[NumRegBanks]);
 }
 
-void RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
+bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
   for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
     const RegisterBank &RegBank = getRegBank(Idx);
     assert(Idx == RegBank.getID() &&
            "ID does not match the index in the array");
     DEBUG(dbgs() << "Verify " << RegBank << '\n');
-    RegBank.verify(TRI);
+    assert(RegBank.verify(TRI) && "RegBank is invalid");
   }
+  return true;
 }
 
 void RegisterBankInfo::createRegisterBank(unsigned ID, const char *Name) {
@@ -344,7 +345,7 @@ RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
     PossibleMappings.emplace_back(std::move(AltMapping));
 #ifndef NDEBUG
   for (const InstructionMapping &Mapping : PossibleMappings)
-    Mapping.verify(MI);
+    assert(Mapping.verify(MI) && "Mapping is invalid");
 #endif
   return PossibleMappings;
 }
@@ -363,12 +364,13 @@ void RegisterBankInfo::PartialMapping::dump() const {
   dbgs() << '\n';
 }
 
-void RegisterBankInfo::PartialMapping::verify() const {
+bool RegisterBankInfo::PartialMapping::verify() const {
   assert(RegBank && "Register bank not set");
   assert(Length && "Empty mapping");
   assert((StartIdx < getHighBitIdx()) && "Overflow, switch to APInt?");
   // Check if the minimum width fits into RegBank.
   assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
+  return true;
 }
 
 void RegisterBankInfo::PartialMapping::print(raw_ostream &OS) const {
@@ -379,13 +381,13 @@ void RegisterBankInfo::PartialMapping::print(raw_ostream &OS) const {
     OS << "nullptr";
 }
 
-void RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const {
+bool RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const {
   assert(!BreakDown.empty() && "Value mapped nowhere?!");
   unsigned OrigValueBitWidth = 0;
   for (const RegisterBankInfo::PartialMapping &PartMap : BreakDown) {
     // Check that each register bank is big enough to hold the partial value:
     // this check is done by PartialMapping::verify
-    PartMap.verify();
+    assert(PartMap.verify() && "Partial mapping is invalid");
     // The original value should completely be mapped.
     // Thus the maximum accessed index + 1 is the size of the original value.
     OrigValueBitWidth =
@@ -404,6 +406,7 @@ void RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const {
            "Some partial mappings overlap");
   }
   assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
+  return true;
 }
 
 void RegisterBankInfo::ValueMapping::dump() const {
@@ -432,7 +435,7 @@ void RegisterBankInfo::InstructionMapping::setOperandMapping(
       PartialMapping(0, MaskSize, RegBank));
 }
 
-void RegisterBankInfo::InstructionMapping::verify(
+bool RegisterBankInfo::InstructionMapping::verify(
     const MachineInstr &MI) const {
   // Check that all the register operands are properly mapped.
   // Check the constructor invariant.
@@ -458,8 +461,9 @@ void RegisterBankInfo::InstructionMapping::verify(
     // Register size in bits.
     // This size must match what the mapping expects.
     unsigned RegSize = getSizeInBits(Reg, MRI, TRI);
-    MOMapping.verify(RegSize);
+    assert(MOMapping.verify(RegSize) && "Value mapping is invalid");
   }
+  return true;
 }
 
 void RegisterBankInfo::InstructionMapping::dump() const {
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index 0a7552bc45d..a877b79c078 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -60,7 +60,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
          "Class not added?");
   assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
 
-  verify(TRI);
+  assert(verify(TRI) && "Invalid register bank information");
 }
 
 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,