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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-24 22:46:53 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-24 22:46:53 +0000 |
commit | c2272df1be0bfdd31a89d2f6ca60bfbf5fd5be50 (patch) | |
tree | 4ae0bbd61a41d927c7365a0f615db4ec729c2136 /llvm | |
parent | 7b838f53a65f6533f7ea5023d6d0c49e5df5319e (diff) | |
download | bcm5719-llvm-c2272df1be0bfdd31a89d2f6ca60bfbf5fd5be50.tar.gz bcm5719-llvm-c2272df1be0bfdd31a89d2f6ca60bfbf5fd5be50.zip |
Infer instruction properties from single-instruction patterns.
Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.
This causes a lot of instruction flags to change.
- Many instructions no longer have the UnmodeledSideEffects flag because
their flags are now inferred from a pattern.
- Instructions with intrinsics will get a mayStore flag if they already
have UnmodeledSideEffects and a mayLoad flag if they already have
mayStore. This is because intrinsics properties are linear.
- Instructions with atomic_load patterns get a mayStore flag because
atomic loads can't be reordered. The correct workaround is to create
pseudo-instructions instead of using normal loads. PR13693.
llvm-svn: 162614
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/test/CodeGen/Hexagon/newvaluejump.ll | 3 | ||||
-rw-r--r-- | llvm/test/CodeGen/Hexagon/newvaluestore.ll | 3 | ||||
-rw-r--r-- | llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 39 |
3 files changed, 45 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump.ll b/llvm/test/CodeGen/Hexagon/newvaluejump.ll index 9c7ca55cb8f..03d36de2955 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump.ll @@ -1,4 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; XFAIL: * +; This is xfailed into we have atomic load pseudos. PR13693. + ; Check that we generate new value jump. @i = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Hexagon/newvaluestore.ll b/llvm/test/CodeGen/Hexagon/newvaluestore.ll index ab69b22df57..a876a949675 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluestore.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluestore.ll @@ -1,4 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; XFAIL: * +; This is xfailed into we have atomic load pseudos. PR13693. + ; Check that we generate new value store packet in V4 @i = global i32 0, align 4 diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp index 7512ae8a25e..52254187d42 100644 --- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp @@ -2383,6 +2383,10 @@ public: AnalyzeNode(Pat->getTree(0)); } + void Analyze(const PatternToMatch *Pat) { + AnalyzeNode(Pat->getSrcPattern()); + } + private: bool IsNodeBitcast(const TreePatternNode *N) const { if (hasSideEffects || mayLoad || mayStore || isVariadic) @@ -2542,6 +2546,17 @@ static bool hasNullFragReference(ListInit *LI) { return false; } +/// Get all the instructions in a tree. +static void +getInstructionsInTree(TreePatternNode *Tree, SmallVectorImpl<Record*> &Instrs) { + if (Tree->isLeaf()) + return; + if (Tree->getOperator()->isSubClassOf("Instruction")) + Instrs.push_back(Tree->getOperator()); + for (unsigned i = 0, e = Tree->getNumChildren(); i != e; ++i) + getInstructionsInTree(Tree->getChild(i), Instrs); +} + /// ParseInstructions - Parse all of the instructions, inlining and resolving /// any fragments involved. This populates the Instructions list with fully /// resolved instructions. @@ -2870,6 +2885,30 @@ void CodeGenDAGPatterns::InferInstructionFlags() { Errors += InferFromPattern(InstInfo, PatInfo, InstInfo.TheDef); } + // Second, look for single-instruction patterns defined outside the + // instruction. + for (ptm_iterator I = ptm_begin(), E = ptm_end(); I != E; ++I) { + const PatternToMatch &PTM = *I; + + // We can only infer from single-instruction patterns, otherwise we won't + // know which instruction should get the flags. + SmallVector<Record*, 8> PatInstrs; + getInstructionsInTree(PTM.getDstPattern(), PatInstrs); + if (PatInstrs.size() != 1) + continue; + + // Get the single instruction. + CodeGenInstruction &InstInfo = Target.getInstruction(PatInstrs.front()); + + // Only infer properties from the first pattern. We'll verify the others. + if (InstInfo.InferredFrom) + continue; + + InstAnalyzer PatInfo(*this); + PatInfo.Analyze(&PTM); + Errors += InferFromPattern(InstInfo, PatInfo, PTM.getSrcRecord()); + } + if (Errors) throw "pattern conflicts"; |