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authorReed Kotler <rkotler@mips.com>2014-04-25 18:05:00 +0000
committerReed Kotler <rkotler@mips.com>2014-04-25 18:05:00 +0000
commitc041669927130a8d08494ff24c08b69f947fd693 (patch)
treec1f887be605ec4af442d1e2b8504d66ac52aae8b /llvm
parent99f0d458c3c52b4c428ec6b5b8b8c457b9dbfae3 (diff)
downloadbcm5719-llvm-c041669927130a8d08494ff24c08b69f947fd693.tar.gz
bcm5719-llvm-c041669927130a8d08494ff24c08b69f947fd693.zip
Make sure that DSUB does not duplicate the pattern of DSUBU
Test Plan: Run test suite to make sure there is no regression. https://dmz-portal.mips.com/bb/builders/LLVM%20with%2064bit%20and%20delay%20slot%20optimizer%20and%20direct%20object%20emitter/builds/626 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3497 llvm-svn: 207247
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/Mips/Mips64InstrInfo.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index e345aa63dfa..81f805ae63a 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -86,7 +86,7 @@ def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
ADD_FM<0, 0x2d>;
def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
ADD_FM<0, 0x2f>;
-def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>;
+def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>;
let isCodeGenOnly = 1 in {
def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
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