diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-08-07 22:00:58 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-08-07 22:00:58 +0000 |
| commit | bd57cea6e49e71f8224111ad8936ac4c1be5fbd5 (patch) | |
| tree | ddfff849acd3a911dd7c7ae7d3d581fa3dd7fb16 /llvm | |
| parent | ad7dc6e31fb9662e0046e3c74b00d075a4e0f3a3 (diff) | |
| download | bcm5719-llvm-bd57cea6e49e71f8224111ad8936ac4c1be5fbd5.tar.gz bcm5719-llvm-bd57cea6e49e71f8224111ad8936ac4c1be5fbd5.zip | |
AMDGPU: Implement getMinimumNopSize
llvm-svn: 310310
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index a50e3eb8d9c..1586914c6c4 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -43,6 +43,8 @@ public: llvm_unreachable("Not implemented"); } bool mayNeedRelaxation(const MCInst &Inst) const override { return false; } + + unsigned getMinimumNopSize() const override; bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; @@ -133,6 +135,10 @@ const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo( return Infos[Kind - FirstTargetFixupKind]; } +unsigned AMDGPUAsmBackend::getMinimumNopSize() const { + return 4; +} + bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { // If the count is not 4-byte aligned, we must be writing data into the text // section (otherwise we have unaligned instructions, and thus have far |
