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| author | Quentin Colombet <qcolombet@apple.com> | 2014-08-18 17:55:43 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2014-08-18 17:55:43 +0000 |
| commit | bd115637424f42d1caa68e7615d610635bae76c8 (patch) | |
| tree | ebe47b9a92fbd0dd8fdc84eaa31d9031690fa597 /llvm | |
| parent | 91513d952227d7576c0efc4e33c9a6d2f79218f5 (diff) | |
| download | bcm5719-llvm-bd115637424f42d1caa68e7615d610635bae76c8.tar.gz bcm5719-llvm-bd115637424f42d1caa68e7615d610635bae76c8.zip | |
[X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer MMX and XMM instructions.
Sub-group: Other instructions.
<rdar://problem/15607571>
llvm-svn: 215917
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 38833de7c25..f998bb6b4db 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -1536,4 +1536,13 @@ def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>; // PSLL,PSRL DQ. def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>; +//-- Other --// + +// EMMS. +def WriteEMMS : SchedWriteRes<[]> { + let Latency = 13; + let NumMicroOps = 31; +} +def : InstRW<[WriteEMMS], (instregex "MMX_EMMS")>; + } // SchedModel |
