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author | Owen Anderson <resistor@mac.com> | 2008-09-04 16:48:33 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2008-09-04 16:48:33 +0000 |
commit | b8c7ba228f49ba5881f1a2634768296ea4a53760 (patch) | |
tree | 55409d27d2cb32e01beb426e0976fedc3c535ed9 /llvm | |
parent | 634412fe35dde3e9da8fb5732aa78cbb1f74f7f4 (diff) | |
download | bcm5719-llvm-b8c7ba228f49ba5881f1a2634768296ea4a53760.tar.gz bcm5719-llvm-b8c7ba228f49ba5881f1a2634768296ea4a53760.zip |
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
llvm-svn: 55777
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/Target/X86/X86FastISel.cpp | 6 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/fast-isel-mem.ll | 2 |
2 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 51ef25a87c6..f46777cd517 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -157,10 +157,10 @@ bool X86FastISel::X86SelectStore(Instruction* I) { X86AddressMode AM; if (Op1) // Address is in register. - AM.Base.Reg = Op0; + AM.Base.Reg = Op1; else AM.GV = cast<GlobalValue>(V); - addFullAddress(BuildMI(MBB, TII.get(Opc)), AM); + addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Op0); return true; } @@ -255,6 +255,8 @@ X86FastISel::TargetSelectInstruction(Instruction *I) { default: break; case Instruction::Load: return X86SelectLoad(I); + case Instruction::Store: + return X86SelectStore(I); } return false; diff --git a/llvm/test/CodeGen/X86/fast-isel-mem.ll b/llvm/test/CodeGen/X86/fast-isel-mem.ll index 5c39fb40170..ca175c48bf3 100644 --- a/llvm/test/CodeGen/X86/fast-isel-mem.ll +++ b/llvm/test/CodeGen/X86/fast-isel-mem.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -fast-isel -mtriple=i386-apple-darwin -mattr=sse2 | \ -; RUN: grep mov | grep lazy_ptr | count 2 +; RUN: grep mov | grep lazy_ptr | count 1 @src = external global i32 |