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authorAditya Nandakumar <aditya_nandakumar@apple.com>2018-03-13 23:21:13 +0000
committerAditya Nandakumar <aditya_nandakumar@apple.com>2018-03-13 23:21:13 +0000
commitb808e3ad8b1e3888f788b44a0684b550bb7ebef9 (patch)
treee23bac5765f6bdf83207f857db4e17d186d57be9 /llvm
parent0d5aa84ad91d8b3c9998efbf4f2e2573a9a2c6cd (diff)
downloadbcm5719-llvm-b808e3ad8b1e3888f788b44a0684b550bb7ebef9.tar.gz
bcm5719-llvm-b808e3ad8b1e3888f788b44a0684b550bb7ebef9.zip
[GISel]: Fix incorrect type used in Pattern Match for ICst
getConstantVRegVal() returns int64_t but we use uint64_t. llvm-svn: 327461
Diffstat (limited to 'llvm')
-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h6
-rw-r--r--llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp10
2 files changed, 8 insertions, 8 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
index 336eba7f979..797f5e542fb 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -43,8 +43,8 @@ inline OneUse_match<SubPat> m_OneUse(const SubPat &SP) {
}
struct ConstantMatch {
- uint64_t &CR;
- ConstantMatch(uint64_t &C) : CR(C) {}
+ int64_t &CR;
+ ConstantMatch(int64_t &C) : CR(C) {}
bool match(const MachineRegisterInfo &MRI, unsigned Reg) {
if (auto MaybeCst = getConstantVRegVal(Reg, MRI)) {
CR = *MaybeCst;
@@ -54,7 +54,7 @@ struct ConstantMatch {
}
};
-inline ConstantMatch m_ICst(uint64_t &Cst) { return ConstantMatch(Cst); }
+inline ConstantMatch m_ICst(int64_t &Cst) { return ConstantMatch(Cst); }
// TODO: Rework this for different kinds of MachineOperand.
// Currently assumes the Src for a match is a register.
diff --git a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
index d402d0b1e11..1084db78180 100644
--- a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
@@ -134,10 +134,10 @@ TEST(PatternMatchInstr, MatchIntConstant) {
MachineRegisterInfo &MRI = MF->getRegInfo();
B.setInsertPt(*EntryMBB, EntryMBB->end());
auto MIBCst = B.buildConstant(LLT::scalar(64), 42);
- uint64_t Cst;
+ int64_t Cst;
bool match = mi_match(MIBCst->getOperand(0).getReg(), MRI, m_ICst(Cst));
ASSERT_TRUE(match);
- ASSERT_EQ(Cst, (uint64_t)42);
+ ASSERT_EQ(Cst, 42);
}
TEST(PatternMatchInstr, MatchBinaryOp) {
@@ -189,11 +189,11 @@ TEST(PatternMatchInstr, MatchBinaryOp) {
auto MIBMul2 = B.buildMul(s64, Copies[0], B.buildConstant(s64, 42));
// Try to match MUL(Cst, Reg) on src of MUL(Reg, Cst) to validate
// commutativity.
- uint64_t Cst;
+ int64_t Cst;
match = mi_match(MIBMul2->getOperand(0).getReg(), MRI,
m_GMul(m_ICst(Cst), m_Reg(Src0)));
ASSERT_TRUE(match);
- ASSERT_EQ(Cst, (uint64_t)42);
+ ASSERT_EQ(Cst, 42);
ASSERT_EQ(Src0, Copies[0]);
// Make sure commutative doesn't work with something like SUB.
@@ -208,7 +208,7 @@ TEST(PatternMatchInstr, MatchBinaryOp) {
match = mi_match(MIBFMul->getOperand(0).getReg(), MRI,
m_GFMul(m_ICst(Cst), m_Reg(Src0)));
ASSERT_TRUE(match);
- ASSERT_EQ(Cst, (uint64_t)42);
+ ASSERT_EQ(Cst, 42);
ASSERT_EQ(Src0, Copies[0]);
// Build AND %0, %1
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