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authorChad Rosier <mcrosier@codeaurora.org>2015-10-01 13:43:05 +0000
committerChad Rosier <mcrosier@codeaurora.org>2015-10-01 13:43:05 +0000
commitb7c5b910682bb1bcaedaa66bcd1c033737175e2e (patch)
treeb23196d6cfd0b549de4b0d6aa12569117f6ecf41 /llvm
parent850d3463029b4d2b8af9b8e7e1e8fbdd4acace6e (diff)
downloadbcm5719-llvm-b7c5b910682bb1bcaedaa66bcd1c033737175e2e.tar.gz
bcm5719-llvm-b7c5b910682bb1bcaedaa66bcd1c033737175e2e.zip
[AArch64] Hoist commonly failing check. NFC.
llvm-svn: 249011
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index e0eb6ad1bc8..178dd248840 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -904,6 +904,12 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
int MIUnscaledOffset = getLdStOffsetOp(MemMI).getImm() * getMemScale(MemMI);
+ // Scan forward looking for post-index opportunities. Updating instructions
+ // can't be formed if the memory instruction doesn't have the offset we're
+ // looking for.
+ if (MIUnscaledOffset != UnscaledOffset)
+ return E;
+
// If the base register overlaps a destination register, we can't
// merge the update.
bool IsPairedInsn = isPairedLdSt(MemMI);
@@ -913,12 +919,6 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
return E;
}
- // Scan forward looking for post-index opportunities. Updating instructions
- // can't be formed if the memory instruction doesn't have the offset we're
- // looking for.
- if (MIUnscaledOffset != UnscaledOffset)
- return E;
-
// Track which registers have been modified and used between the first insn
// (inclusive) and the second insn.
BitVector ModifiedRegs, UsedRegs;
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