diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 23:51:33 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 23:51:33 +0000 |
| commit | b249b7572686172dd0a44292f5b5fe9bdf8aad8d (patch) | |
| tree | 70842c05b725e9f71430a3e98eb40f0b8fb284e0 /llvm | |
| parent | ad3aff246cde02bbc3977ba09eba960b7998e54e (diff) | |
| download | bcm5719-llvm-b249b7572686172dd0a44292f5b5fe9bdf8aad8d.tar.gz bcm5719-llvm-b249b7572686172dd0a44292f5b5fe9bdf8aad8d.zip | |
R600: Expand vector FRINT ops
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 188598
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/llvm.rint.ll | 54 |
2 files changed, 55 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index cab07da288c..dd8b73f00d5 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -154,6 +154,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FDIV, VT, Expand); setOperationAction(ISD::FFLOOR, VT, Expand); setOperationAction(ISD::FMUL, VT, Expand); + setOperationAction(ISD::FRINT, VT, Expand); setOperationAction(ISD::FSUB, VT, Expand); } } diff --git a/llvm/test/CodeGen/R600/llvm.rint.ll b/llvm/test/CodeGen/R600/llvm.rint.ll new file mode 100644 index 00000000000..c1bbc237df8 --- /dev/null +++ b/llvm/test/CodeGen/R600/llvm.rint.ll @@ -0,0 +1,54 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK: @f32 +; R600-CHECK: RNDNE +; SI-CHECK: @f32 +; SI-CHECK: V_RNDNE_F32_e32 +define void @f32(float addrspace(1)* %out, float %in) { +entry: + %0 = call float @llvm.rint.f32(float %in) + store float %0, float addrspace(1)* %out + ret void +} + +; R600-CHECK: @v2f32 +; R600-CHECK: RNDNE +; R600-CHECK: RNDNE +; SI-CHECK: @v2f32 +; SI-CHECK: V_RNDNE_F32_e32 +; SI-CHECK: V_RNDNE_F32_e32 +define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %0 = call <2 x float> @llvm.rint.v2f32(<2 x float> %in) + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; R600-CHECK: @v4f32 +; R600-CHECK: RNDNE +; R600-CHECK: RNDNE +; R600-CHECK: RNDNE +; R600-CHECK: RNDNE +; SI-CHECK: @v4f32 +; SI-CHECK: V_RNDNE_F32_e32 +; SI-CHECK: V_RNDNE_F32_e32 +; SI-CHECK: V_RNDNE_F32_e32 +; SI-CHECK: V_RNDNE_F32_e32 +define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %0 = call <4 x float> @llvm.rint.v4f32(<4 x float> %in) + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} + +; Function Attrs: nounwind readonly +declare float @llvm.rint.f32(float) #0 + +; Function Attrs: nounwind readonly +declare <2 x float> @llvm.rint.v2f32(<2 x float>) #0 + +; Function Attrs: nounwind readonly +declare <4 x float> @llvm.rint.v4f32(<4 x float>) #0 + +attributes #0 = { nounwind readonly } |
