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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-01-31 22:54:27 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-01-31 22:54:27 +0000 |
| commit | af88f0eb448c0113589e73e21342bca61585dca0 (patch) | |
| tree | 500ba820c69c9146f5fc0f7f3ee6092af52439df /llvm | |
| parent | b86b771c020725e7f2113898e841a6f29b919548 (diff) | |
| download | bcm5719-llvm-af88f0eb448c0113589e73e21342bca61585dca0.tar.gz bcm5719-llvm-af88f0eb448c0113589e73e21342bca61585dca0.zip | |
AMDGPU: Fix missing SCC def from s_xor_b64_term
llvm-svn: 323927
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 9740a18b724..f87b4f4fda6 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -186,6 +186,7 @@ def S_XOR_B64_term : PseudoInstSI<(outs SReg_64:$dst), let SALU = 1; let isAsCheapAsAMove = 1; let isTerminator = 1; + let Defs = [SCC]; } def S_ANDN2_B64_term : PseudoInstSI<(outs SReg_64:$dst), |
