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author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-08-09 05:48:01 +0000 |
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committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-08-09 05:48:01 +0000 |
commit | ad3453cf2d235b8fdbbef92be4951ca29c0a2521 (patch) | |
tree | 5ccaa67571b9007d9d52ce19e73708ef28c50652 /llvm | |
parent | dee205a31ee237df1b162ba68d635d3f3405e103 (diff) | |
download | bcm5719-llvm-ad3453cf2d235b8fdbbef92be4951ca29c0a2521.tar.gz bcm5719-llvm-ad3453cf2d235b8fdbbef92be4951ca29c0a2521.zip |
Handle sitofp between v4f64 <- v4i32. Fix PR10559
llvm-svn: 137114
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 22 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/avx-cvt.ll | 7 |
2 files changed, 28 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 71b23e2ccb0..b8197edb2b1 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -969,6 +969,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); + // sint_to_fp between different vector types needs custom handling + setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom); + setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); @@ -7078,6 +7081,24 @@ SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const { EVT SrcVT = Op.getOperand(0).getValueType(); + EVT DstVT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); + + if (SrcVT.isVector() && DstVT.isVector()) { + unsigned SrcVTSize = SrcVT.getSizeInBits(); + unsigned DstVTSize = DstVT.getSizeInBits(); + + // Support directly by the target + if (SrcVTSize == DstVTSize) + return Op; + + // Handle v4f64 = sitofp v4i32 + if (DstVT != MVT::v4f64 && SrcVT != MVT::v4i32) + return SDValue(); + + SDValue V = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Op.getOperand(0)); + return DAG.getNode(ISD::FP_EXTEND, dl, DstVT, V); + } if (SrcVT.isVector()) return SDValue(); @@ -7094,7 +7115,6 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, return Op; } - DebugLoc dl = Op.getDebugLoc(); unsigned Size = SrcVT.getSizeInBits()/8; MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); diff --git a/llvm/test/CodeGen/X86/avx-cvt.ll b/llvm/test/CodeGen/X86/avx-cvt.ll index e45010c903e..5fe207e0600 100644 --- a/llvm/test/CodeGen/X86/avx-cvt.ll +++ b/llvm/test/CodeGen/X86/avx-cvt.ll @@ -6,6 +6,13 @@ define <8 x float> @sitofp00(<8 x i32> %a) nounwind { ret <8 x float> %b } +; CHECK: vcvtdq2ps +; CHECK-NEXT: vcvtps2pd +define <4 x double> @sitofp01(<4 x i32> %a) { + %b = sitofp <4 x i32> %a to <4 x double> + ret <4 x double> %b +} + ; CHECK: vcvttps2dq %ymm define <8 x i32> @fptosi00(<8 x float> %a) nounwind { %b = fptosi <8 x float> %a to <8 x i32> |