summaryrefslogtreecommitdiffstats
path: root/llvm
diff options
context:
space:
mode:
authorZoran Jovanovic <zoran.jovanovic@imgtec.com>2014-09-12 13:43:41 +0000
committerZoran Jovanovic <zoran.jovanovic@imgtec.com>2014-09-12 13:43:41 +0000
commitac9ef12fc5c10dc0486c5ed75536b229dffd56a1 (patch)
tree32567a28de1260de14e79d81c18323f0d713f260 /llvm
parent4e7ac4ad2a2c66c5a4e7f82c3c0f219a42a25f5b (diff)
downloadbcm5719-llvm-ac9ef12fc5c10dc0486c5ed75536b229dffd56a1.tar.gz
bcm5719-llvm-ac9ef12fc5c10dc0486c5ed75536b229dffd56a1.zip
[mips][microMIPS] Implement JALS and JALRS instructions.
Differential Revision: http://reviews.llvm.org/D5003 llvm-svn: 217676
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp24
-rw-r--r--llvm/lib/Target/Mips/MicroMipsInstrInfo.td17
-rw-r--r--llvm/test/MC/Mips/micromips-jump-instructions.s10
3 files changed, 47 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 14e98494b1e..1a5aed47b32 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -981,6 +981,16 @@ static const MCInstrDesc &getInstDesc(unsigned Opcode) {
return MipsInsts[Opcode];
}
+static bool hasShortDelaySlot(unsigned Opcode) {
+ switch (Opcode) {
+ case Mips::JALS_MM:
+ case Mips::JALRS_MM:
+ return true;
+ default:
+ return false;
+ }
+}
+
bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
@@ -1050,10 +1060,16 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
// emit a NOP after it.
Instructions.push_back(Inst);
MCInst NopInst;
- NopInst.setOpcode(Mips::SLL);
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateImm(0));
+ if (hasShortDelaySlot(Inst.getOpcode())) {
+ NopInst.setOpcode(Mips::MOVE16_MM);
+ NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ } else {
+ NopInst.setOpcode(Mips::SLL);
+ NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::CreateImm(0));
+ }
Instructions.push_back(NopInst);
return false;
}
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index 4ffa74439fe..dbbf1602919 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -104,6 +104,19 @@ class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
let Defs = [RA];
}
+// MicroMIPS Jump and Link (Call) - Short Delay Slot
+let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
+ class JumpLinkMM<string opstr, DAGOperand opnd> :
+ InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
+ [], IIBranch, FrmJ, opstr> {
+ let DecoderMethod = "DecodeJumpTargetMM";
+ }
+
+ class JumpLinkRegMM<string opstr, RegisterOperand RO>:
+ InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
+ [], IIBranch, FrmR>;
+}
+
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
@@ -263,6 +276,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
+ /// Jump Instructions - Short Delay Slot
+ def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
+ def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
+
/// Branch Instructions
def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
BEQ_FM_MM<0x25>;
diff --git a/llvm/test/MC/Mips/micromips-jump-instructions.s b/llvm/test/MC/Mips/micromips-jump-instructions.s
index a6c7676f809..aed18dc2074 100644
--- a/llvm/test/MC/Mips/micromips-jump-instructions.s
+++ b/llvm/test/MC/Mips/micromips-jump-instructions.s
@@ -19,6 +19,10 @@
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EL: jr $7 # encoding: [0x07,0x00,0x3c,0x0f]
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EL: jals 1328 # encoding: [0x00,0x74,0x98,0x02]
+# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c]
+# CHECK-EL: jalrs $ra, $6 # encoding: [0xe6,0x03,0x3c,0x4f]
+# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@@ -32,9 +36,15 @@
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EB: jr $7 # encoding: [0x00,0x07,0x0f,0x3c]
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-EB: jals 1328 # encoding: [0x74,0x00,0x02,0x98]
+# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00]
+# CHECK-EB: jalrs $ra, $6 # encoding: [0x03,0xe6,0x4f,0x3c]
+# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00]
j 1328
jal 1328
jalr $ra, $6
jr $7
j $7
+ jals 1328
+ jalrs $ra, $6
OpenPOWER on IntegriCloud