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authorQuentin Colombet <qcolombet@apple.com>2016-04-08 17:19:10 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-04-08 17:19:10 +0000
commitab8c21f72bb02a136e0c4a540bff7da83f9b2ee7 (patch)
tree96137cbed9bba8813c75f15b05f4c490324350e7 /llvm
parentbd19c8a39ee66bb508a7311071fc2e08f2f34c63 (diff)
downloadbcm5719-llvm-ab8c21f72bb02a136e0c4a540bff7da83f9b2ee7.tar.gz
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[RegBankSelect] Use reverse post order traversal.
When assigning the register banks of an instruction, it is best to know all the constraints of the input to have a good idea of how this will impact the cost of the whole function. llvm-svn: 265812
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp14
1 files changed, 12 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index f417193fdeb..71687884f4d 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -10,6 +10,7 @@
/// This file implements the RegBankSelect class.
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -125,6 +126,12 @@ void RegBankSelect::assignInstr(MachineInstr &MI) {
// This will not hold when we will consider alternative mappings.
DEBUG(dbgs() << "Assign: " << *ValMapping.BreakDown[0].RegBank << " to "
<< PrintReg(Reg) << '\n');
+ // For a definition, we may be changing the register bank silently
+ // for all the uses here.
+ // Although this will be correct when we do a RPO traversal of the
+ // basic block, because the only uses that could be affected are
+ // PHIs (i.e., copies), this may not be the best solution
+ // according to the cost model.
MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank);
MO.setReg(Reg);
}
@@ -135,8 +142,11 @@ bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
init(MF);
// Walk the function and assign register banks to all operands.
- for (MachineBasicBlock &MBB : MF)
- for (MachineInstr &MI : MBB)
+ // Use a RPOT to make sure all registers are assigned before we choose
+ // the best mapping of the current instruction.
+ ReversePostOrderTraversal<MachineFunction*> RPOT(&MF);
+ for (MachineBasicBlock *MBB : RPOT)
+ for (MachineInstr &MI : *MBB)
assignInstr(MI);
return false;
}
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