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author | Tim Northover <tnorthover@apple.com> | 2019-10-04 12:29:32 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2019-10-04 12:29:32 +0000 |
commit | a7d90af1be48234ce583e00fb16e33633d44ae38 (patch) | |
tree | e4d1907366f419f7197d8edd73707edde6136a7c /llvm | |
parent | e64369e76ea4f4f1bd33c6453f42b4b83bbb9fe3 (diff) | |
download | bcm5719-llvm-a7d90af1be48234ce583e00fb16e33633d44ae38.tar.gz bcm5719-llvm-a7d90af1be48234ce583e00fb16e33633d44ae38.zip |
ARM-Darwin: keep the frame register reserved even if not updated.
Darwin platforms need the frame register to always point at a valid record even
if it's not updated in a leaf function. Backtraces are more important than one
extra GPR.
llvm-svn: 373738
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/ARM/r7-fixed-darwin.ll | 15 | ||||
-rw-r--r-- | llvm/test/CodeGen/Thumb/long.ll | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll | 2 |
4 files changed, 18 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 46382816b98..1eaf871867e 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -191,7 +191,7 @@ getReservedRegs(const MachineFunction &MF) const { markSuperRegs(Reserved, ARM::PC); markSuperRegs(Reserved, ARM::FPSCR); markSuperRegs(Reserved, ARM::APSR_NZCV); - if (TFI->hasFP(MF)) + if (TFI->hasFP(MF) || STI.isTargetDarwin()) markSuperRegs(Reserved, getFramePointerReg(STI)); if (hasBasePointer(MF)) markSuperRegs(Reserved, BasePtr); diff --git a/llvm/test/CodeGen/ARM/r7-fixed-darwin.ll b/llvm/test/CodeGen/ARM/r7-fixed-darwin.ll new file mode 100644 index 00000000000..dc59b6acb42 --- /dev/null +++ b/llvm/test/CodeGen/ARM/r7-fixed-darwin.ll @@ -0,0 +1,15 @@ +; RUN: llc -mtriple=thumbv7k-apple-watchos %s -o - | FileCheck %s + +; r7 is FP on Darwin, and should be preserved even if we don't create a new +; frame record for this leaf function. So make huge register pressure to try & +; tempt LLVM to use it. +define void @foo([16 x i32]* %ptr) { +; CHECK-LABEL: foo: +; CHECK: push.w +; CHECK: .cfi_offset r7 +; CHECK-NOT: r7 +; CHECK: pop.w + %val = load volatile [16 x i32], [16 x i32]* %ptr + store volatile [16 x i32] %val, [16 x i32]* %ptr + ret void +} diff --git a/llvm/test/CodeGen/Thumb/long.ll b/llvm/test/CodeGen/Thumb/long.ll index fbf4b08fd06..856196af71f 100644 --- a/llvm/test/CodeGen/Thumb/long.ll +++ b/llvm/test/CodeGen/Thumb/long.ll @@ -234,7 +234,7 @@ if.end: %c = add i64 %y, 47 call void @f13(i64 %c) ; CHECK: adds -; CHECK-NEXT: adcs +; CHECK: adcs ; CHECK: bl ret void } diff --git a/llvm/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll b/llvm/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll index b28f4542cf3..b00554af680 100644 --- a/llvm/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll +++ b/llvm/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll @@ -17,7 +17,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- ; CHECK: bl _f2 ; CHECK: clz {{r[0-9]+}} ; CHECK-DAG: lsrs {{r[0-9]+}} -; CHECK-DAG: lsls {{r[0-9]+}} +; CHECK-DAG: lsl.w {{r[0-9]+}} ; CHECK-NEXT: orr.w {{r[0-9]+}} ; CHECK-NEXT: InlineAsm Start define void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { |