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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-18 18:41:41 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-18 18:41:41 +0000 |
| commit | a3b3b489fbb08d100ef3213b29616ae4f964c4ac (patch) | |
| tree | 500b4349c1c8b934e6361f3143ae57f510186b88 /llvm | |
| parent | e823d92f7fb170d40d8c40e062accd398b60d2f6 (diff) | |
| download | bcm5719-llvm-a3b3b489fbb08d100ef3213b29616ae4f964c4ac.tar.gz bcm5719-llvm-a3b3b489fbb08d100ef3213b29616ae4f964c4ac.zip | |
AMDGPU: Fix disassembly of aperture registers
llvm-svn: 295555
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/aperture-regs.ll | 13 |
2 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 5733b9cace1..ff95a9b23af 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -523,6 +523,11 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { case 124: return createRegOperand(M0); case 126: return createRegOperand(EXEC_LO); case 127: return createRegOperand(EXEC_HI); + case 235: return createRegOperand(SRC_SHARED_BASE); + case 236: return createRegOperand(SRC_SHARED_LIMIT); + case 237: return createRegOperand(SRC_PRIVATE_BASE); + case 238: return createRegOperand(SRC_PRIVATE_LIMIT); + // TODO: SRC_POPS_EXITING_WAVE_ID // ToDo: no support for vccz register case 251: break; // ToDo: no support for execz register diff --git a/llvm/test/MC/Disassembler/AMDGPU/aperture-regs.ll b/llvm/test/MC/Disassembler/AMDGPU/aperture-regs.ll new file mode 100644 index 00000000000..5fec281145b --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/aperture-regs.ll @@ -0,0 +1,13 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX9 %s + +# GFX9: v_mov_b32_e32 v1, src_shared_base ; encoding: [0xeb,0x02,0x02,0x7e] +0xeb 0x02 0x02 0x7e + +# GFX9: v_mov_b32_e32 v1, src_shared_limit ; encoding: [0xec,0x02,0x02,0x7e] +0xec 0x02 0x02 0x7e + +# GFX9: v_mov_b32_e32 v1, src_private_base ; encoding: [0xed,0x02,0x02,0x7e] +0xed 0x02 0x02 0x7e + +# GFX9: v_mov_b32_e32 v1, src_private_limit ; encoding: [0xee,0x02,0x02,0x7e] +0xee 0x02 0x02 0x7e |
