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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-10 17:44:47 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-10 17:44:47 +0000 |
| commit | a39da09eb667e16299bbbe2dee556b121c87c6fe (patch) | |
| tree | 7fd49d2d96cd1fe0212503966f610720da6628b0 /llvm | |
| parent | 497311ab99dd9996c7869590c2fd83e9b1a57919 (diff) | |
| download | bcm5719-llvm-a39da09eb667e16299bbbe2dee556b121c87c6fe.tar.gz bcm5719-llvm-a39da09eb667e16299bbbe2dee556b121c87c6fe.zip | |
R600/SI: Disable copying of SCC
llvm-svn: 219519
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.td | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.td b/llvm/lib/Target/R600/SIRegisterInfo.td index 7e00a73ba13..799810db005 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.td +++ b/llvm/lib/Target/R600/SIRegisterInfo.td @@ -170,7 +170,11 @@ def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, //===----------------------------------------------------------------------===// // Special register classes for predicates and the M0 register -def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>; +def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> { + let CopyCost = -1; // Theoretically it is possible to read from SCC, + // but it should never be necessary. +} + def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>; def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>; def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>; |
