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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-27 03:39:27 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-27 03:39:27 +0000 |
| commit | a15ea4e217ddc4929f806eb27f49a61d9d6acc84 (patch) | |
| tree | 2803fd65ef3a8429d1745ee77ed415ae20f2bb11 /llvm | |
| parent | 71ed8a67e874367025385533057fc4e287a5ded7 (diff) | |
| download | bcm5719-llvm-a15ea4e217ddc4929f806eb27f49a61d9d6acc84.tar.gz bcm5719-llvm-a15ea4e217ddc4929f806eb27f49a61d9d6acc84.zip | |
AMDGPU: Mark sched model complete
Fixes bug 26800
llvm-svn: 279910
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SISchedule.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td index ed19217226b..0db92fc254f 100644 --- a/llvm/lib/Target/AMDGPU/SISchedule.td +++ b/llvm/lib/Target/AMDGPU/SISchedule.td @@ -46,7 +46,7 @@ def Write64Bit : SchedWrite; // instructions) class SISchedMachineModel : SchedMachineModel { - let CompleteModel = 0; + let CompleteModel = 1; let IssueWidth = 1; let PostRAScheduler = 1; } |
