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| author | Jessica Paquette <jpaquette@apple.com> | 2019-01-28 18:34:16 +0000 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2019-01-28 18:34:16 +0000 |
| commit | 9f6afad9136fb2e43a6a61be99946e93089433ba (patch) | |
| tree | ac073e27e89f17e5d8a017c8c8d0f662f14d95bf /llvm | |
| parent | 3d1d95ca55741cae5568991f05cd79de5d396d21 (diff) | |
| download | bcm5719-llvm-9f6afad9136fb2e43a6a61be99946e93089433ba.tar.gz bcm5719-llvm-9f6afad9136fb2e43a6a61be99946e93089433ba.zip | |
[GlobalISel] Add G_FSIN and G_FCOS generic instructions
This introduces generic instrutions for floating point sin and cos, G_FCOS and
G_FSIN. It updates the tests, etc.
https://reviews.llvm.org/D57197
1/3
llvm-svn: 352400
Diffstat (limited to 'llvm')
4 files changed, 29 insertions, 1 deletions
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 0d5e3f3beb2..553db2e4c20 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -520,6 +520,12 @@ HANDLE_TARGET_OPCODE(G_BSWAP) /// Floating point ceil. HANDLE_TARGET_OPCODE(G_FCEIL) +/// Floating point cosine. +HANDLE_TARGET_OPCODE(G_FCOS) + +/// Floating point sine. +HANDLE_TARGET_OPCODE(G_FSIN) + /// Generic AddressSpaceCast. HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index 3f0f81a0f21..639ca1b8a09 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -555,6 +555,20 @@ def G_FCEIL : GenericInstruction { let hasSideEffects = 0; } +// Floating point cosine of a value. +def G_FCOS : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + +// Floating point sine of a value. +def G_FSIN : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + //------------------------------------------------------------------------------ // Opcodes for LLVM Intrinsics //------------------------------------------------------------------------------ diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index c3223ea66f3..f5179b6c915 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -89,6 +89,8 @@ def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>; def : GINodeEquiv<G_CTPOP, ctpop>; def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>; def : GINodeEquiv<G_FCEIL, fceil>; +def : GINodeEquiv<G_FCOS, fcos>; +def : GINodeEquiv<G_FSIN, fsin>; // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some // complications that tablegen must take care of. For example, Predicates such diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index d74762aa275..8cf750c1154 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -331,7 +331,13 @@ # DEBUG: .. the first uncovered type index: 1, OK # # DEBUG-NEXT: G_FCEIL (opcode {{[0-9]+}}): 1 type index -# DEBUG: .. the first uncovered type index: 1, OK +# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_FCOS (opcode {{[0-9]+}}): 1 type index +# DEBUG: .. type index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_FSIN (opcode {{[0-9]+}}): 1 type index +# DEBUG: .. type index coverage check SKIPPED: no rules defined # CHECK-NOT: ill-defined |
