diff options
| author | Krzysztof Parzyszek <kparzysz@quicinc.com> | 2019-03-06 17:43:50 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@quicinc.com> | 2019-03-06 17:43:50 +0000 |
| commit | 9c005bbdd4db8e0395c34211d3b1adf77bc0e9ee (patch) | |
| tree | 7c48fb71ca2e57647edd082c00011f4df78c7a63 /llvm | |
| parent | 1b6700eff4a928ea2f01fe74f9f902d9324e2551 (diff) | |
| download | bcm5719-llvm-9c005bbdd4db8e0395c34211d3b1adf77bc0e9ee.tar.gz bcm5719-llvm-9c005bbdd4db8e0395c34211d3b1adf77bc0e9ee.zip | |
[Hexagon] Avoid creating 5-instruction packets with vgather pseudos
Change the resource usage of the vgather pseudos from SLOT0+LD to
SLOT0+SLOT1.
llvm-svn: 355524
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonIICHVX.td | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/packetize-vgather-slot01.mir | 22 |
2 files changed, 29 insertions, 5 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonIICHVX.td b/llvm/lib/Target/Hexagon/HexagonIICHVX.td index 1d71d60bf58..06e9c83cf30 100644 --- a/llvm/lib/Target/Hexagon/HexagonIICHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonIICHVX.td @@ -16,12 +16,14 @@ class HVXItin { InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>, - // Used by Gather Pseudo Instructions which are expanded into - // V6_vgather* and V6_vS32b_new_ai. Even though these instructions - // use CVI_ST resource, it's not included below to avoid having more than - // 4 InstrStages and thus changing 'MaxResTerms' to 5. + // Used by gather pseudo-instructions which are expanded into V6_vgather* + // and V6_vS32b_new_ai. Even though these instructions use CVI_LD resource, + // it's not included below to avoid having more than 4 InstrStages and + // thus changing 'MaxResTerms' to 5. Instead, both SLOT0 and SLOT1 are + // used, which should be sufficient. InstrItinData <CVI_GATHER_PSEUDO, [InstrStage<1, [SLOT0], 0>, - InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>]; } diff --git a/llvm/test/CodeGen/Hexagon/packetize-vgather-slot01.mir b/llvm/test/CodeGen/Hexagon/packetize-vgather-slot01.mir new file mode 100644 index 00000000000..5271b8535b2 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/packetize-vgather-slot01.mir @@ -0,0 +1,22 @@ +# RUN: llc -march=hexagon -mcpu=hexagonv65 -mattr=+hvxv65,+hvx-length64b -run-pass=hexagon-packetizer -o - %s | FileCheck %s + +# Check that we don't generate a packet with 5 instructions. + +# CHECK: BUNDLE +# CHECK-NEXT: V6_vaslw_acc +# CHECK-NEXT: V6_vgathermw +# CHECK-NEXT: V6_vS32b_new_ai +# CHECK-NEXT: A2_addi +# CHECK-NEXT: } + +name: fred +tracksRegLiveness: true +body: | + bb.0: + liveins: $r0, $r1, $r2, $r3, $m0, $v0, $v1, $v2 + $v0 = V6_vaslw_acc $v0, killed $v1, $r0 + V6_vgathermw_pseudo $r1, $r2, $m0, killed $v2 + $r4 = A2_addi $r1, 512 + $r5 = A2_addi $r1, 640 + V6_vgathermw_pseudo killed $r3, $r2, $m0, killed $v0 +... |

