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| author | Craig Topper <craig.topper@intel.com> | 2017-11-19 01:25:30 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-11-19 01:25:30 +0000 |
| commit | 9a94dfc457443b263ded785722bdd085cb05ab22 (patch) | |
| tree | 1b0c2daa212ecc731d2592c2e970e537fd4a5a9c /llvm | |
| parent | 81037f385e346da03c94eadd9fa336e1ab3ea2cc (diff) | |
| download | bcm5719-llvm-9a94dfc457443b263ded785722bdd085cb05ab22.tar.gz bcm5719-llvm-9a94dfc457443b263ded785722bdd085cb05ab22.zip | |
[X86] Switch cannonlake to use the SkylakeServer scheduling model instead of Haswell.
Cannonlake comes after skylake and supports avx512 so this is probably a closer model for now.
llvm-svn: 318613
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sha-schedule.ll | 14 |
2 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 573d4413717..62aab840258 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -658,7 +658,7 @@ def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [ FeatureSHA ]>; -class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel, +class CannonlakeProc<string Name> : ProcModel<Name, SkylakeServerModel, CNLFeatures.Value, [ ProcIntelCNL ]>; diff --git a/llvm/test/CodeGen/X86/sha-schedule.ll b/llvm/test/CodeGen/X86/sha-schedule.ll index e33495415e2..3f1cad276bf 100644 --- a/llvm/test/CodeGen/X86/sha-schedule.ll +++ b/llvm/test/CodeGen/X86/sha-schedule.ll @@ -25,7 +25,7 @@ define <4 x i32> @test_sha1msg1(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { ; CANNONLAKE: # BB#0: ; CANNONLAKE-NEXT: sha1msg1 %xmm1, %xmm0 ; CANNONLAKE-NEXT: sha1msg1 (%rdi), %xmm0 -; CANNONLAKE-NEXT: retq # sched: [2:1.00] +; CANNONLAKE-NEXT: retq # sched: [7:1.00] ; ; ZNVER1-LABEL: test_sha1msg1: ; ZNVER1: # BB#0: @@ -56,7 +56,7 @@ define <4 x i32> @test_sha1msg2(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { ; CANNONLAKE: # BB#0: ; CANNONLAKE-NEXT: sha1msg2 %xmm1, %xmm0 ; CANNONLAKE-NEXT: sha1msg2 (%rdi), %xmm0 -; CANNONLAKE-NEXT: retq # sched: [2:1.00] +; CANNONLAKE-NEXT: retq # sched: [7:1.00] ; ; ZNVER1-LABEL: test_sha1msg2: ; ZNVER1: # BB#0: @@ -87,7 +87,7 @@ define <4 x i32> @test_sha1nexte(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { ; CANNONLAKE: # BB#0: ; CANNONLAKE-NEXT: sha1nexte %xmm1, %xmm0 ; CANNONLAKE-NEXT: sha1nexte (%rdi), %xmm0 -; CANNONLAKE-NEXT: retq # sched: [2:1.00] +; CANNONLAKE-NEXT: retq # sched: [7:1.00] ; ; ZNVER1-LABEL: test_sha1nexte: ; ZNVER1: # BB#0: @@ -118,7 +118,7 @@ define <4 x i32> @test_sha1rnds4(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { ; CANNONLAKE: # BB#0: ; CANNONLAKE-NEXT: sha1rnds4 $3, %xmm1, %xmm0 ; CANNONLAKE-NEXT: sha1rnds4 $3, (%rdi), %xmm0 -; CANNONLAKE-NEXT: retq # sched: [2:1.00] +; CANNONLAKE-NEXT: retq # sched: [7:1.00] ; ; ZNVER1-LABEL: test_sha1rnds4: ; ZNVER1: # BB#0: @@ -153,7 +153,7 @@ define <4 x i32> @test_sha256msg1(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) ; CANNONLAKE: # BB#0: ; CANNONLAKE-NEXT: sha256msg1 %xmm1, %xmm0 ; CANNONLAKE-NEXT: sha256msg1 (%rdi), %xmm0 -; CANNONLAKE-NEXT: retq # sched: [2:1.00] +; CANNONLAKE-NEXT: retq # sched: [7:1.00] ; ; ZNVER1-LABEL: test_sha256msg1: ; ZNVER1: # BB#0: @@ -184,7 +184,7 @@ define <4 x i32> @test_sha256msg2(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) ; CANNONLAKE: # BB#0: ; CANNONLAKE-NEXT: sha256msg2 %xmm1, %xmm0 ; CANNONLAKE-NEXT: sha256msg2 (%rdi), %xmm0 -; CANNONLAKE-NEXT: retq # sched: [2:1.00] +; CANNONLAKE-NEXT: retq # sched: [7:1.00] ; ; ZNVER1-LABEL: test_sha256msg2: ; ZNVER1: # BB#0: @@ -224,7 +224,7 @@ define <4 x i32> @test_sha256rnds2(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, ; CANNONLAKE-NEXT: sha256rnds2 %xmm0, %xmm1, %xmm3 ; CANNONLAKE-NEXT: sha256rnds2 %xmm0, (%rdi), %xmm3 ; CANNONLAKE-NEXT: vmovaps %xmm3, %xmm0 # sched: [1:1.00] -; CANNONLAKE-NEXT: retq # sched: [2:1.00] +; CANNONLAKE-NEXT: retq # sched: [7:1.00] ; ; ZNVER1-LABEL: test_sha256rnds2: ; ZNVER1: # BB#0: |
